1 /*
2 * Copyright 2018-2019 NXP
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <command.h>
9 #include <cpu_func.h>
10 #include <hang.h>
11 #include <image.h>
12 #include <init.h>
13 #include <log.h>
14 #include <spl.h>
15 #include <asm/global_data.h>
16 #include <asm/io.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/imx8mn_pins.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/mach-imx/boot_mode.h>
22 #include <asm/arch/ddr.h>
23
24 #include <dm/uclass.h>
25 #include <dm/device.h>
26 #include <dm/uclass-internal.h>
27 #include <dm/device-internal.h>
28
29 DECLARE_GLOBAL_DATA_PTR;
30
spl_board_boot_device(enum boot_device boot_dev_spl)31 int spl_board_boot_device(enum boot_device boot_dev_spl)
32 {
33 return BOOT_DEVICE_BOOTROM;
34 }
35
spl_dram_init(void)36 void spl_dram_init(void)
37 {
38 ddr_init(&dram_timing);
39 }
40
spl_board_init(void)41 void spl_board_init(void)
42 {
43 struct udevice *dev;
44 int ret;
45
46 puts("Normal Boot\n");
47
48 ret = uclass_get_device_by_name(UCLASS_CLK,
49 "clock-controller@30380000",
50 &dev);
51 if (ret < 0)
52 printf("Failed to find clock node. Check device tree\n");
53 }
54
55 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)56 int board_fit_config_name_match(const char *name)
57 {
58 /* Just empty function now - can't decide what to choose */
59 debug("%s: %s\n", __func__, name);
60
61 return 0;
62 }
63 #endif
64
65 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
66 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
67
68 static iomux_v3_cfg_t const uart_pads[] = {
69 IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
70 IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
71 };
72
73 static iomux_v3_cfg_t const wdog_pads[] = {
74 IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
75 };
76
board_early_init_f(void)77 int board_early_init_f(void)
78 {
79 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
80
81 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
82
83 set_wdog_reset(wdog);
84
85 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
86
87 init_uart_clk(1);
88
89 return 0;
90 }
91
board_init_f(ulong dummy)92 void board_init_f(ulong dummy)
93 {
94 int ret;
95
96 arch_cpu_init();
97
98 init_uart_clk(1);
99
100 board_early_init_f();
101
102 timer_init();
103
104 preloader_console_init();
105
106 /* Clear the BSS. */
107 memset(__bss_start, 0, __bss_end - __bss_start);
108
109 ret = spl_init();
110 if (ret) {
111 debug("spl_init() failed: %d\n", ret);
112 hang();
113 }
114
115 enable_tzc380();
116
117 /* DDR initialization */
118 spl_dram_init();
119
120 board_init_r(NULL, 0);
121 }
122