1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2019 NXP
4 */
5
6 #include <common.h>
7 #include <env.h>
8 #include <errno.h>
9 #include <init.h>
10 #include <miiphy.h>
11 #include <netdev.h>
12 #include <linux/delay.h>
13 #include <asm/global_data.h>
14 #include <asm/mach-imx/iomux-v3.h>
15 #include <asm-generic/gpio.h>
16 #include <asm/arch/imx8mp_pins.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/mach-imx/gpio.h>
20
21 DECLARE_GLOBAL_DATA_PTR;
22
23 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
24 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
25
26 static iomux_v3_cfg_t const uart_pads[] = {
27 MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
28 MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
29 };
30
31 static iomux_v3_cfg_t const wdog_pads[] = {
32 MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
33 };
34
board_early_init_f(void)35 int board_early_init_f(void)
36 {
37 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
38
39 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
40
41 set_wdog_reset(wdog);
42
43 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
44
45 return 0;
46 }
47
setup_fec(void)48 static void setup_fec(void)
49 {
50 struct iomuxc_gpr_base_regs *gpr =
51 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
52
53 /* Enable RGMII TX clk output */
54 setbits_le32(&gpr->gpr[1], BIT(22));
55 }
56
57 #define EQOS_RST_PAD IMX_GPIO_NR(4, 22)
58 static iomux_v3_cfg_t const eqos_rst_pads[] = {
59 MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
60 };
61
setup_iomux_eqos(void)62 static void setup_iomux_eqos(void)
63 {
64 imx_iomux_v3_setup_multiple_pads(eqos_rst_pads,
65 ARRAY_SIZE(eqos_rst_pads));
66
67 gpio_request(EQOS_RST_PAD, "eqos_rst");
68 gpio_direction_output(EQOS_RST_PAD, 0);
69 mdelay(15);
70 gpio_direction_output(EQOS_RST_PAD, 1);
71 mdelay(100);
72 }
73
setup_eqos(void)74 static int setup_eqos(void)
75 {
76 struct iomuxc_gpr_base_regs *gpr =
77 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
78
79 setup_iomux_eqos();
80
81 /* set INTF as RGMII, enable RGMII TXC clock */
82 clrsetbits_le32(&gpr->gpr[1],
83 IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
84 setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
85
86 return set_clk_eqos(ENET_125MHZ);
87 }
88
89 #if CONFIG_IS_ENABLED(NET)
board_phy_config(struct phy_device * phydev)90 int board_phy_config(struct phy_device *phydev)
91 {
92 if (phydev->drv->config)
93 phydev->drv->config(phydev);
94 return 0;
95 }
96 #endif
97
board_init(void)98 int board_init(void)
99 {
100 int ret = 0;
101
102 if (CONFIG_IS_ENABLED(FEC_MXC)) {
103 setup_fec();
104
105 if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
106 ret = setup_eqos();
107 }
108
109 return ret;
110 }
111
board_late_init(void)112 int board_late_init(void)
113 {
114 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
115 env_set("board_name", "EVK");
116 env_set("board_rev", "iMX8MP");
117 #endif
118
119 return 0;
120 }
121