1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2018 NXP
4 */
5
6 #include <common.h>
7 #include <env.h>
8 #include <init.h>
9 #include <malloc.h>
10 #include <errno.h>
11 #include <asm/global_data.h>
12 #include <asm/io.h>
13 #include <miiphy.h>
14 #include <netdev.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm-generic/gpio.h>
17 #include <fsl_esdhc_imx.h>
18 #include <mmc.h>
19 #include <asm/arch/imx8mq_pins.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/mach-imx/gpio.h>
22 #include <asm/mach-imx/mxc_i2c.h>
23 #include <asm/arch/clock.h>
24 #include <spl.h>
25 #include <linux/bitops.h>
26 #include <power/pmic.h>
27 #include <power/pfuze100_pmic.h>
28 #include "../common/pfuze.h"
29
30 DECLARE_GLOBAL_DATA_PTR;
31
32 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
33
34 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
35
36 static iomux_v3_cfg_t const wdog_pads[] = {
37 IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
38 };
39
40 static iomux_v3_cfg_t const uart_pads[] = {
41 IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
42 IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
43 };
44
board_early_init_f(void)45 int board_early_init_f(void)
46 {
47 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
48
49 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
50 set_wdog_reset(wdog);
51
52 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
53
54 return 0;
55 }
56
57 #ifdef CONFIG_FEC_MXC
setup_fec(void)58 static int setup_fec(void)
59 {
60 struct iomuxc_gpr_base_regs *gpr =
61 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
62
63 /* Use 125M anatop REF_CLK1 for ENET1, not from external */
64 clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
65 return set_clk_enet(ENET_125MHZ);
66 }
67
board_phy_config(struct phy_device * phydev)68 int board_phy_config(struct phy_device *phydev)
69 {
70 /* enable rgmii rxc skew and phy mode select to RGMII copper */
71 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
72 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
73
74 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
75 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
76
77 if (phydev->drv->config)
78 phydev->drv->config(phydev);
79 return 0;
80 }
81 #endif
82
board_init(void)83 int board_init(void)
84 {
85 #ifdef CONFIG_FEC_MXC
86 setup_fec();
87 #endif
88
89 return 0;
90 }
91
board_mmc_get_env_dev(int devno)92 int board_mmc_get_env_dev(int devno)
93 {
94 return devno;
95 }
96
board_late_init(void)97 int board_late_init(void)
98 {
99 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
100 env_set("board_name", "EVK");
101 env_set("board_rev", "iMX8MQ");
102 #endif
103
104 return 0;
105 }
106