1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2016 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <i2c.h>
8 #include <fdt_support.h>
9 #include <asm/cache.h>
10 #include <init.h>
11 #include <asm/global_data.h>
12 #include <asm/io.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/fsl_serdes.h>
15 #ifdef CONFIG_FSL_LS_PPA
16 #include <asm/arch/ppa.h>
17 #endif
18 #include <asm/arch/fdt.h>
19 #include <asm/arch/mmu.h>
20 #include <asm/arch/soc.h>
21 #include <ahci.h>
22 #include <hwconfig.h>
23 #include <mmc.h>
24 #include <env_internal.h>
25 #include <scsi.h>
26 #include <fm_eth.h>
27 #include <fsl_esdhc.h>
28 #include <fsl_mmdc.h>
29 #include <spl.h>
30 #include <netdev.h>
31 #include <fsl_sec.h>
32 #include "../common/qixis.h"
33 #include "ls1012aqds_qixis.h"
34 #include "ls1012aqds_pfe.h"
35
36 DECLARE_GLOBAL_DATA_PTR;
37
checkboard(void)38 int checkboard(void)
39 {
40 char buf[64];
41 u8 sw;
42
43 sw = QIXIS_READ(arch);
44 printf("Board Arch: V%d, ", sw >> 4);
45 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
46
47 sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
48
49 if (sw & QIXIS_LBMAP_ALTBANK)
50 printf("flash: 2\n");
51 else
52 printf("flash: 1\n");
53
54 printf("FPGA: v%d (%s), build %d",
55 (int)QIXIS_READ(scver), qixis_read_tag(buf),
56 (int)qixis_read_minor());
57
58 /* the timestamp string contains "\n" at the end */
59 printf(" on %s", qixis_read_time(buf));
60 return 0;
61 }
62
63 #ifdef CONFIG_TFABOOT
dram_init(void)64 int dram_init(void)
65 {
66 gd->ram_size = tfa_get_dram_size();
67 if (!gd->ram_size)
68 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
69
70 return 0;
71 }
72 #else
dram_init(void)73 int dram_init(void)
74 {
75 static const struct fsl_mmdc_info mparam = {
76 0x05180000, /* mdctl */
77 0x00030035, /* mdpdc */
78 0x12554000, /* mdotc */
79 0xbabf7954, /* mdcfg0 */
80 0xdb328f64, /* mdcfg1 */
81 0x01ff00db, /* mdcfg2 */
82 0x00001680, /* mdmisc */
83 0x0f3c8000, /* mdref */
84 0x00002000, /* mdrwd */
85 0x00bf1023, /* mdor */
86 0x0000003f, /* mdasp */
87 0x0000022a, /* mpodtctrl */
88 0xa1390003, /* mpzqhwctrl */
89 };
90
91 mmdc_init(&mparam);
92 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
93 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
94 /* This will break-before-make MMU for DDR */
95 update_early_mmu_table();
96 #endif
97
98 return 0;
99 }
100 #endif
101
board_early_init_f(void)102 int board_early_init_f(void)
103 {
104 fsl_lsch2_early_init_f();
105
106 return 0;
107 }
108
109 #ifdef CONFIG_MISC_INIT_R
misc_init_r(void)110 int misc_init_r(void)
111 {
112 u8 mux_sdhc_cd = 0x80;
113 int bus_num = 0;
114
115 #if CONFIG_IS_ENABLED(DM_I2C)
116 struct udevice *dev;
117 int ret;
118
119 ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_FPGA_ADDR,
120 1, &dev);
121 if (ret) {
122 printf("%s: Cannot find udev for a bus %d\n", __func__,
123 bus_num);
124 return ret;
125 }
126 dm_i2c_write(dev, 0x5a, &mux_sdhc_cd, 1);
127 #else
128 i2c_set_bus_num(bus_num);
129
130 i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
131 #endif
132
133 return 0;
134 }
135 #endif
136
board_init(void)137 int board_init(void)
138 {
139 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
140 CONFIG_SYS_CCI400_OFFSET);
141
142 /* Set CCI-400 control override register to enable barrier
143 * transaction */
144 if (current_el() == 3)
145 out_le32(&cci->ctrl_ord,
146 CCI400_CTRLORD_EN_BARRIER);
147
148 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
149 erratum_a010315();
150 #endif
151
152 #ifdef CONFIG_ENV_IS_NOWHERE
153 gd->env_addr = (ulong)&default_environment[0];
154 #endif
155
156 #ifdef CONFIG_FSL_CAAM
157 sec_init();
158 #endif
159
160 #ifdef CONFIG_FSL_LS_PPA
161 ppa_init();
162 #endif
163 return 0;
164 }
165
esdhc_status_fixup(void * blob,const char * compat)166 int esdhc_status_fixup(void *blob, const char *compat)
167 {
168 char esdhc0_path[] = "/soc/esdhc@1560000";
169 char esdhc1_path[] = "/soc/esdhc@1580000";
170 u8 card_id;
171
172 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
173 sizeof("okay"), 1);
174
175 /*
176 * The Presence Detect 2 register detects the installation
177 * of cards in various PCI Express or SGMII slots.
178 *
179 * STAT_PRS2[7:5]: Specifies the type of card installed in the
180 * SDHC2 Adapter slot. 0b111 indicates no adapter is installed.
181 */
182 card_id = (QIXIS_READ(present2) & 0xe0) >> 5;
183
184 /* If no adapter is installed in SDHC2, disable SDHC2 */
185 if (card_id == 0x7)
186 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
187 sizeof("disabled"), 1);
188 else
189 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
190 sizeof("okay"), 1);
191 return 0;
192 }
193
pfe_set_properties(void * set_blob,struct pfe_prop_val prop_val,char * enet_path,char * mdio_path)194 static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val,
195 char *enet_path, char *mdio_path)
196 {
197 do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id",
198 &prop_val.busid, PFE_PROP_LEN, 1);
199 do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id",
200 &prop_val.phyid, PFE_PROP_LEN, 1);
201 do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val",
202 &prop_val.mux_val, PFE_PROP_LEN, 1);
203 do_fixup_by_path(set_blob, enet_path, "phy-mode",
204 prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1);
205 do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask",
206 &prop_val.phy_mask, PFE_PROP_LEN, 1);
207 return 0;
208 }
209
fdt_fsl_fixup_of_pfe(void * blob)210 static void fdt_fsl_fixup_of_pfe(void *blob)
211 {
212 int i = 0;
213 struct pfe_prop_val prop_val;
214 void *l_blob = blob;
215
216 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
217 unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
218 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
219 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
220
221 for (i = 0; i < NUM_ETH_NODE; i++) {
222 switch (srds_s1) {
223 case SERDES_1_G_PROTOCOL:
224 if (i == 0) {
225 prop_val.busid = cpu_to_fdt32(
226 ETH_1_1G_BUS_ID);
227 prop_val.phyid = cpu_to_fdt32(
228 ETH_1_1G_PHY_ID);
229 prop_val.mux_val = cpu_to_fdt32(
230 ETH_1_1G_MDIO_MUX);
231 prop_val.phy_mask = cpu_to_fdt32(
232 ETH_1G_MDIO_PHY_MASK);
233 prop_val.phy_mode = "sgmii";
234 pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
235 ETH_1_MDIO);
236 } else {
237 prop_val.busid = cpu_to_fdt32(
238 ETH_2_1G_BUS_ID);
239 prop_val.phyid = cpu_to_fdt32(
240 ETH_2_1G_PHY_ID);
241 prop_val.mux_val = cpu_to_fdt32(
242 ETH_2_1G_MDIO_MUX);
243 prop_val.phy_mask = cpu_to_fdt32(
244 ETH_1G_MDIO_PHY_MASK);
245 prop_val.phy_mode = "rgmii";
246 pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
247 ETH_2_MDIO);
248 }
249 break;
250 case SERDES_2_5_G_PROTOCOL:
251 if (i == 0) {
252 prop_val.busid = cpu_to_fdt32(
253 ETH_1_2_5G_BUS_ID);
254 prop_val.phyid = cpu_to_fdt32(
255 ETH_1_2_5G_PHY_ID);
256 prop_val.mux_val = cpu_to_fdt32(
257 ETH_1_2_5G_MDIO_MUX);
258 prop_val.phy_mask = cpu_to_fdt32(
259 ETH_2_5G_MDIO_PHY_MASK);
260 prop_val.phy_mode = "sgmii-2500";
261 pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
262 ETH_1_MDIO);
263 } else {
264 prop_val.busid = cpu_to_fdt32(
265 ETH_2_2_5G_BUS_ID);
266 prop_val.phyid = cpu_to_fdt32(
267 ETH_2_2_5G_PHY_ID);
268 prop_val.mux_val = cpu_to_fdt32(
269 ETH_2_2_5G_MDIO_MUX);
270 prop_val.phy_mask = cpu_to_fdt32(
271 ETH_2_5G_MDIO_PHY_MASK);
272 prop_val.phy_mode = "sgmii-2500";
273 pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
274 ETH_2_MDIO);
275 }
276 break;
277 default:
278 printf("serdes:[%d]\n", srds_s1);
279 }
280 }
281 }
282
283 #ifdef CONFIG_OF_BOARD_SETUP
ft_board_setup(void * blob,struct bd_info * bd)284 int ft_board_setup(void *blob, struct bd_info *bd)
285 {
286 arch_fixup_fdt(blob);
287
288 ft_cpu_setup(blob, bd);
289 fdt_fsl_fixup_of_pfe(blob);
290
291 return 0;
292 }
293 #endif
294