1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2016 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <clock_legacy.h>
8 #include <fdt_support.h>
9 #include <init.h>
10 #include <net.h>
11 #include <asm/arch/immap_ls102xa.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/fsl_serdes.h>
14 #include <asm/arch/ls102xa_stream_id.h>
15 #include <asm/global_data.h>
16 #include <linux/delay.h>
17
18 #include <asm/arch/ls102xa_devdis.h>
19 #include <asm/arch/ls102xa_soc.h>
20 #include <fsl_csu.h>
21 #include <fsl_immap.h>
22 #include <netdev.h>
23 #include <fsl_mdio.h>
24 #include <tsec.h>
25 #include <spl.h>
26
27 #include <fsl_validate.h>
28 #include "../common/sleep.h"
29
30 DECLARE_GLOBAL_DATA_PTR;
31
32 #define DDR_SIZE 0x40000000
33
34
checkboard(void)35 int checkboard(void)
36 {
37 puts("Board: LS1021AIOT\n");
38
39 #ifndef CONFIG_QSPI_BOOT
40 struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
41 u32 cpldrev;
42
43 cpldrev = in_be32(&dcfg->gpporcr1);
44
45 printf("CPLD: V%d.%d\n", ((cpldrev >> 28) & 0xf), ((cpldrev >> 24) &
46 0xf));
47 #endif
48 return 0;
49 }
50
ddrmc_init(void)51 void ddrmc_init(void)
52 {
53 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
54 u32 temp_sdram_cfg, tmp;
55
56 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
57
58 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
59 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
60
61 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
62 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
63 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
64 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
65 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
66 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
67
68 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
69 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
70
71 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
72 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
73
74 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
75
76 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
77
78 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
79 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
80
81 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
82
83 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
84 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
85
86 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
87
88 /* DDR erratum A-009942 */
89 tmp = in_be32(&ddr->debug[28]);
90 out_be32(&ddr->debug[28], tmp | 0x0070006f);
91
92 udelay(500);
93
94 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
95
96 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
97 }
98
dram_init(void)99 int dram_init(void)
100 {
101 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
102 ddrmc_init();
103 #endif
104
105 erratum_a008850_post();
106
107 gd->ram_size = DDR_SIZE;
108 return 0;
109 }
110
111 #ifdef CONFIG_TSEC_ENET
board_eth_init(struct bd_info * bis)112 int board_eth_init(struct bd_info *bis)
113 {
114 struct fsl_pq_mdio_info mdio_info;
115 struct tsec_info_struct tsec_info[4];
116 int num = 0;
117
118 #ifdef CONFIG_TSEC1
119 SET_STD_TSEC_INFO(tsec_info[num], 1);
120 if (is_serdes_configured(SGMII_TSEC1)) {
121 puts("eTSEC1 is in sgmii mode.\n");
122 tsec_info[num].flags |= TSEC_SGMII;
123 }
124 num++;
125 #endif
126 #ifdef CONFIG_TSEC2
127 SET_STD_TSEC_INFO(tsec_info[num], 2);
128 if (is_serdes_configured(SGMII_TSEC2)) {
129 puts("eTSEC2 is in sgmii mode.\n");
130 tsec_info[num].flags |= TSEC_SGMII;
131 }
132 num++;
133 #endif
134 if (!num) {
135 printf("No TSECs initialized\n");
136 return 0;
137 }
138
139 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
140 mdio_info.name = DEFAULT_MII_NAME;
141 fsl_pq_mdio_init(bis, &mdio_info);
142
143 tsec_eth_init(bis, tsec_info, num);
144
145 return pci_eth_init(bis);
146 }
147 #endif
148
board_early_init_f(void)149 int board_early_init_f(void)
150 {
151 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
152
153 #ifdef CONFIG_TSEC_ENET
154 /* clear BD & FR bits for BE BD's and frame data */
155 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
156 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
157
158 #endif
159
160 arch_soc_init();
161
162 return 0;
163 }
164
165 #ifdef CONFIG_SPL_BUILD
board_init_f(ulong dummy)166 void board_init_f(ulong dummy)
167 {
168 /* Clear the BSS */
169 memset(__bss_start, 0, __bss_end - __bss_start);
170
171 get_clocks();
172
173 preloader_console_init();
174
175 dram_init();
176
177 /* Allow OCRAM access permission as R/W */
178
179 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
180 enable_layerscape_ns_access();
181 #endif
182
183 board_init_r(NULL, 0);
184 }
185 #endif
186
board_init(void)187 int board_init(void)
188 {
189 #ifndef CONFIG_SYS_FSL_NO_SERDES
190 fsl_serdes_init();
191 #endif
192
193 ls102xa_smmu_stream_id_init();
194
195 return 0;
196 }
197
198 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)199 int board_late_init(void)
200 {
201 return 0;
202 }
203 #endif
204
205 #if defined(CONFIG_MISC_INIT_R)
misc_init_r(void)206 int misc_init_r(void)
207 {
208 #ifdef CONFIG_FSL_DEVICE_DISABLE
209 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
210
211 #endif
212
213 #ifdef CONFIG_FSL_CAAM
214 return sec_init();
215 #endif
216 }
217 #endif
218
ft_board_setup(void * blob,struct bd_info * bd)219 int ft_board_setup(void *blob, struct bd_info *bd)
220 {
221 ft_cpu_setup(blob, bd);
222
223 #ifdef CONFIG_PCI
224 ft_pci_setup(blob, bd);
225 #endif
226
227 return 0;
228 }
229
flash_write16(u16 val,void * addr)230 void flash_write16(u16 val, void *addr)
231 {
232 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
233
234 __raw_writew(shftval, addr);
235 }
236
flash_read16(void * addr)237 u16 flash_read16(void *addr)
238 {
239 u16 val = __raw_readw(addr);
240
241 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
242 }
243