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..18-Mar-2022-

Kconfig A D18-Mar-2022639 3223

MAINTAINERS A D18-Mar-2022592 1716

Makefile A D18-Mar-2022190 116

README A D18-Mar-20222.7 KiB7771

cpld.c A D18-Mar-20223.5 KiB167125

cpld.h A D18-Mar-20221.7 KiB5035

ddr.c A D18-Mar-20223 KiB13492

ddr.h A D18-Mar-20221.6 KiB6335

eth.c A D18-Mar-20223.1 KiB13091

ls1046ardb.c A D18-Mar-20223.8 KiB187138

ls1046ardb_pbi.cfg A D18-Mar-2022416 2322

ls1046ardb_qspi_pbi.cfg A D18-Mar-2022481 2726

ls1046ardb_rcw_emmc.cfg A D18-Mar-2022197 87

ls1046ardb_rcw_qspi.cfg A D18-Mar-2022197 87

ls1046ardb_rcw_sd.cfg A D18-Mar-2022197 87

README

1Overview
2--------
3The LS1046A Reference Design Board (RDB) is a high-performance computing,
4evaluation, and development platform that supports the QorIQ LS1046A
5LayerScape Architecture processor. The LS1046ARDB provides SW development
6platform for the Freescale LS1046A processor series, with a complete
7debugging environment. The LS1046A RDB is lead-free and RoHS-compliant.
8
9LS1046A SoC Overview
10--------------------
11Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A
12SoC overview.
13
14 LS1046ARDB board Overview
15 -----------------------
16 - SERDES1 Connections, 4 lanes supporting:
17      - Lane0: XFI with x1 RJ45 connector
18      - Lane1: XFI Cage
19      - Lane2: SGMII.5
20      - Lane3: SGMII.6
21 - SERDES2 Connections, 4 lanes supporting:
22      - Lane0: PCIe1 with miniPCIe slot
23      - Lane1: PCIe2 with PCIe x2 slot
24      - Lane2: PCIe3 with PCIe x4 slot
25      - Lane3: SATA
26 - DDR Controller
27     - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
28 -IFC/Local Bus
29    - One 512 MB NAND flash with ECC support
30    - CPLD connection
31 - USB 3.0
32    - one Type A port, one Micro-AB port
33 - SDHC: connects directly to a full SD/MMC slot
34 - DSPI: 64 MB high-speed flash Memory for boot code and storage (up to 108MHz)
35 - 4 I2C controllers
36 - UART
37   - Two 4-pin serial ports at up to 115.2 Kbit/s
38   - Two DB9 D-Type connectors supporting one Serial port each
39 - ARM JTAG support
40
41Memory map from core's view
42----------------------------
43Start Address	 End Address	 Description		Size
440x00_0000_0000 - 0x00_000F_FFFF  Secure Boot ROM	1MB
450x00_0100_0000 - 0x00_0FFF_FFFF  CCSRBAR		240MB
460x00_1000_0000 - 0x00_1000_FFFF  OCRAM0 		64KB
470x00_1001_0000 - 0x00_1001_FFFF  OCRAM1 		64KB
480x00_2000_0000 - 0x00_20FF_FFFF  DCSR			16MB
490x00_7E80_0000 - 0x00_7E80_FFFF  IFC - NAND Flash	64KB
500x00_7FB0_0000 - 0x00_7FB0_0FFF  IFC - CPLD		4KB
510x00_8000_0000 - 0x00_FFFF_FFFF  DRAM1			2GB
520x05_0000_0000 - 0x05_07FF_FFFF  QMAN S/W Portal	128M
530x05_0800_0000 - 0x05_0FFF_FFFF  BMAN S/W Portal	128M
540x08_8000_0000 - 0x09_FFFF_FFFF  DRAM2			6GB
550x40_0000_0000 - 0x47_FFFF_FFFF  PCI Express1		32G
560x48_0000_0000 - 0x4F_FFFF_FFFF  PCI Express2		32G
570x50_0000_0000 - 0x57_FFFF_FFFF  PCI Express3		32G
58
59QSPI flash map:
60Start Address    End Address     Description		Size
610x00_4000_0000 - 0x00_400F_FFFF  RCW + PBI		1MB
620x00_4010_0000 - 0x00_402F_FFFF  U-Boot 		2MB
630x00_4030_0000 - 0x00_403F_FFFF  U-Boot Env		1MB
640x00_4040_0000 - 0x00_405F_FFFF  PPA			2MB
650x00_4060_0000 - 0x00_408F_FFFF  Secure boot header
66				 + bootscript		3MB
670x00_4090_0000 - 0x00_4093_FFFF  FMan ucode		256KB
680x00_4094_0000 - 0x00_4097_FFFF  QE/uQE firmware	256KB
690x00_4098_0000 - 0x00_40FF_FFFF  Reserved		6MB
700x00_4100_0000 - 0x00_43FF_FFFF  FIT Image		48MB
71
72Booting Options
73---------------
74a) QSPI boot
75b) SD boot
76c) eMMC boot
77