1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2016 Freescale Semiconductor, Inc.
4  */
5 
6 #ifndef __DDR_H__
7 #define __DDR_H__
8 
9 void erratum_a008850_post(void);
10 
11 struct board_specific_parameters {
12 	u32 n_ranks;
13 	u32 datarate_mhz_high;
14 	u32 rank_gb;
15 	u32 clk_adjust;
16 	u32 wrlvl_start;
17 	u32 wrlvl_ctl_2;
18 	u32 wrlvl_ctl_3;
19 };
20 
21 /*
22  * These tables contain all valid speeds we want to override with board
23  * specific parameters. datarate_mhz_high values need to be in ascending order
24  * for each n_ranks group.
25  */
26 static const struct board_specific_parameters udimm0[] = {
27 	/*
28 	 * memory controller 0
29 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
30 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
31 	 */
32 	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
33 	{2,  1666, 0, 8,     7, 0x08090A0C, 0x0D0F100B,},
34 	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
35 	{2,  2300, 0, 8,     7, 0x08090A0E, 0x1011120C,},
36 	{}
37 };
38 
39 static const struct board_specific_parameters *udimms[] = {
40 	udimm0,
41 };
42 
43 static const struct board_specific_parameters rdimm0[] = {
44 	/*
45 	 * memory controller 0
46 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
47 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
48 	 */
49 	{2,  1666, 0, 0x8,     0x0D, 0x0C0B0A08, 0x0A0B0C08,},
50 	{2,  1900, 0, 0x8,     0x0E, 0x0D0C0B09, 0x0B0C0D09,},
51 	{2,  2300, 0, 0xa,     0x12, 0x100F0D0C, 0x0E0F100C,},
52 	{1,  1666, 0, 0x8,     0x0D, 0x0C0B0A08, 0x0A0B0C08,},
53 	{1,  1900, 0, 0x8,     0x0E, 0x0D0C0B09, 0x0B0C0D09,},
54 	{1,  2300, 0, 0xa,     0x12, 0x100F0D0C, 0x0E0F100C,},
55 	{}
56 };
57 
58 static const struct board_specific_parameters *rdimms[] = {
59 	rdimm0,
60 };
61 
62 #endif
63