1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2016 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <i2c.h>
8 #include <fdt_support.h>
9 #include <init.h>
10 #include <asm/global_data.h>
11 #include <asm/io.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/fsl_serdes.h>
14 #include <asm/arch/ppa.h>
15 #include <asm/arch/soc.h>
16 #include <asm/arch-fsl-layerscape/fsl_icid.h>
17 #include <hwconfig.h>
18 #include <ahci.h>
19 #include <mmc.h>
20 #include <scsi.h>
21 #include <fm_eth.h>
22 #include <fsl_csu.h>
23 #include <fsl_esdhc.h>
24 #include <power/mc34vr500_pmic.h>
25 #include "cpld.h"
26 #include <fsl_sec.h>
27
28 DECLARE_GLOBAL_DATA_PTR;
29
board_early_init_f(void)30 int board_early_init_f(void)
31 {
32 fsl_lsch2_early_init_f();
33
34 return 0;
35 }
36
37 #ifndef CONFIG_SPL_BUILD
checkboard(void)38 int checkboard(void)
39 {
40 static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
41 u8 cfg_rcw_src1, cfg_rcw_src2;
42 u16 cfg_rcw_src;
43 u8 sd1refclk_sel;
44
45 puts("Board: LS1046ARDB, boot from ");
46
47 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
48 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
49 cpld_rev_bit(&cfg_rcw_src1);
50 cfg_rcw_src = cfg_rcw_src1;
51 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
52
53 if (cfg_rcw_src == 0x44)
54 printf("QSPI vBank %d\n", CPLD_READ(vbank));
55 else if (cfg_rcw_src == 0x40)
56 puts("SD\n");
57 else
58 puts("Invalid setting of SW5\n");
59
60 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
61 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
62
63 puts("SERDES Reference Clocks:\n");
64 sd1refclk_sel = CPLD_READ(sd1refclk_sel);
65 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
66
67 return 0;
68 }
69
board_init(void)70 int board_init(void)
71 {
72 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
73
74 #ifdef CONFIG_NXP_ESBC
75 /*
76 * In case of Secure Boot, the IBR configures the SMMU
77 * to allow only Secure transactions.
78 * SMMU must be reset in bypass mode.
79 * Set the ClientPD bit and Clear the USFCFG Bit
80 */
81 u32 val;
82 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
83 out_le32(SMMU_SCR0, val);
84 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
85 out_le32(SMMU_NSCR0, val);
86 #endif
87
88 #ifdef CONFIG_FSL_CAAM
89 sec_init();
90 #endif
91
92 #ifdef CONFIG_FSL_LS_PPA
93 ppa_init();
94 #endif
95
96 /* invert AQR105 IRQ pins polarity */
97 out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
98
99 return 0;
100 }
101
board_setup_core_volt(u32 vdd)102 int board_setup_core_volt(u32 vdd)
103 {
104 bool en_0v9;
105
106 en_0v9 = (vdd == 900) ? true : false;
107 cpld_select_core_volt(en_0v9);
108
109 return 0;
110 }
111
get_serdes_volt(void)112 int get_serdes_volt(void)
113 {
114 return mc34vr500_get_sw_volt(SW4);
115 }
116
set_serdes_volt(int svdd)117 int set_serdes_volt(int svdd)
118 {
119 return mc34vr500_set_sw_volt(SW4, svdd);
120 }
121
power_init_board(void)122 int power_init_board(void)
123 {
124 int ret;
125
126 ret = power_mc34vr500_init(0);
127 if (ret)
128 return ret;
129
130 setup_chip_volt();
131
132 return 0;
133 }
134
config_board_mux(void)135 void config_board_mux(void)
136 {
137 #ifdef CONFIG_HAS_FSL_XHCI_USB
138 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
139 u32 usb_pwrfault;
140
141 /* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */
142 out_be32(&scfg->rcwpmuxcr0, 0x3300);
143 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
144 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
145 SCFG_USBPWRFAULT_USB3_SHIFT) |
146 (SCFG_USBPWRFAULT_DEDICATED <<
147 SCFG_USBPWRFAULT_USB2_SHIFT) |
148 (SCFG_USBPWRFAULT_SHARED <<
149 SCFG_USBPWRFAULT_USB1_SHIFT);
150 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
151 #endif
152 }
153
154 #ifdef CONFIG_MISC_INIT_R
misc_init_r(void)155 int misc_init_r(void)
156 {
157 config_board_mux();
158 return 0;
159 }
160 #endif
161
ft_board_setup(void * blob,struct bd_info * bd)162 int ft_board_setup(void *blob, struct bd_info *bd)
163 {
164 u64 base[CONFIG_NR_DRAM_BANKS];
165 u64 size[CONFIG_NR_DRAM_BANKS];
166
167 /* fixup DT for the two DDR banks */
168 base[0] = gd->bd->bi_dram[0].start;
169 size[0] = gd->bd->bi_dram[0].size;
170 base[1] = gd->bd->bi_dram[1].start;
171 size[1] = gd->bd->bi_dram[1].size;
172
173 fdt_fixup_memory_banks(blob, base, size, 2);
174 ft_cpu_setup(blob, bd);
175
176 #ifdef CONFIG_SYS_DPAA_FMAN
177 #ifndef CONFIG_DM_ETH
178 fdt_fixup_fman_ethernet(blob);
179 #endif
180 #endif
181
182 fdt_fixup_icid(blob);
183
184 return 0;
185 }
186 #endif
187