1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015 Freescale Semiconductor
4 * Copyright 2017 NXP
5 */
6 #include <common.h>
7 #include <env.h>
8 #include <init.h>
9 #include <malloc.h>
10 #include <errno.h>
11 #include <netdev.h>
12 #include <fsl_ifc.h>
13 #include <fsl_ddr.h>
14 #include <asm/global_data.h>
15 #include <asm/io.h>
16 #include <hwconfig.h>
17 #include <fdt_support.h>
18 #include <linux/libfdt.h>
19 #include <fsl-mc/fsl_mc.h>
20 #include <env_internal.h>
21 #include <efi_loader.h>
22 #include <i2c.h>
23 #include <asm/arch/mmu.h>
24 #include <asm/arch/soc.h>
25 #include <asm/arch/ppa.h>
26 #include <fsl_sec.h>
27 #include <asm/arch-fsl-layerscape/fsl_icid.h>
28
29 #ifdef CONFIG_FSL_QIXIS
30 #include "../common/qixis.h"
31 #include "ls2080ardb_qixis.h"
32 #endif
33 #include "../common/vid.h"
34
35 #define PIN_MUX_SEL_SDHC 0x00
36 #define PIN_MUX_SEL_DSPI 0x0a
37
38 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
39 DECLARE_GLOBAL_DATA_PTR;
40
41 enum {
42 MUX_TYPE_SDHC,
43 MUX_TYPE_DSPI,
44 };
45
46 #ifdef CONFIG_VID
soc_get_fuse_vid(int vid_index)47 u16 soc_get_fuse_vid(int vid_index)
48 {
49 static const u16 vdd[32] = {
50 10500,
51 0, /* reserved */
52 9750,
53 0, /* reserved */
54 9500,
55 0, /* reserved */
56 0, /* reserved */
57 0, /* reserved */
58 9000, /* reserved */
59 0, /* reserved */
60 0, /* reserved */
61 0, /* reserved */
62 0, /* reserved */
63 0, /* reserved */
64 0, /* reserved */
65 0, /* reserved */
66 10000, /* 1.0000V */
67 0, /* reserved */
68 10250,
69 0, /* reserved */
70 10500,
71 0, /* reserved */
72 0, /* reserved */
73 0, /* reserved */
74 0, /* reserved */
75 0, /* reserved */
76 0, /* reserved */
77 0, /* reserved */
78 0, /* reserved */
79 0, /* reserved */
80 0, /* reserved */
81 0, /* reserved */
82 };
83
84 return vdd[vid_index];
85 };
86 #endif
87
get_qixis_addr(void)88 unsigned long long get_qixis_addr(void)
89 {
90 unsigned long long addr;
91
92 if (gd->flags & GD_FLG_RELOC)
93 addr = QIXIS_BASE_PHYS;
94 else
95 addr = QIXIS_BASE_PHYS_EARLY;
96
97 /*
98 * IFC address under 256MB is mapped to 0x30000000, any address above
99 * is mapped to 0x5_10000000 up to 4GB.
100 */
101 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
102
103 return addr;
104 }
105
checkboard(void)106 int checkboard(void)
107 {
108 #ifdef CONFIG_FSL_QIXIS
109 u8 sw;
110 #endif
111 char buf[15];
112
113 cpu_name(buf);
114 printf("Board: %s-RDB, ", buf);
115
116 #ifdef CONFIG_TARGET_LS2081ARDB
117 #ifdef CONFIG_FSL_QIXIS
118 sw = QIXIS_READ(arch);
119 printf("Board version: %c, ", (sw & 0xf) + 'A');
120
121 sw = QIXIS_READ(brdcfg[0]);
122 sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK;
123 switch (sw) {
124 case 0:
125 puts("boot from QSPI DEV#0\n");
126 puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
127 break;
128 case 1:
129 puts("boot from QSPI DEV#1\n");
130 puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
131 break;
132 case 2:
133 puts("boot from QSPI EMU\n");
134 puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
135 break;
136 case 3:
137 puts("boot from QSPI EMU\n");
138 puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
139 break;
140 case 4:
141 puts("boot from QSPI DEV#0\n");
142 puts("QSPI_CSA_1 mapped to QSPI EMU\n");
143 break;
144 default:
145 printf("invalid setting of SW%u\n", sw);
146 break;
147 }
148 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
149 #endif
150 puts("SERDES1 Reference : ");
151 printf("Clock1 = 100MHz ");
152 printf("Clock2 = 161.13MHz");
153 #else
154 #ifdef CONFIG_FSL_QIXIS
155 sw = QIXIS_READ(arch);
156 printf("Board Arch: V%d, ", sw >> 4);
157 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
158
159 sw = QIXIS_READ(brdcfg[0]);
160 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
161
162 if (sw < 0x8)
163 printf("vBank: %d\n", sw);
164 else if (sw == 0x9)
165 puts("NAND\n");
166 else
167 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
168
169 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
170 #endif
171 puts("SERDES1 Reference : ");
172 printf("Clock1 = 156.25MHz ");
173 printf("Clock2 = 156.25MHz");
174 #endif
175
176 puts("\nSERDES2 Reference : ");
177 printf("Clock1 = 100MHz ");
178 printf("Clock2 = 100MHz\n");
179
180 return 0;
181 }
182
get_board_sys_clk(void)183 unsigned long get_board_sys_clk(void)
184 {
185 #ifdef CONFIG_FSL_QIXIS
186 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
187
188 switch (sysclk_conf & 0x0F) {
189 case QIXIS_SYSCLK_83:
190 return 83333333;
191 case QIXIS_SYSCLK_100:
192 return 100000000;
193 case QIXIS_SYSCLK_125:
194 return 125000000;
195 case QIXIS_SYSCLK_133:
196 return 133333333;
197 case QIXIS_SYSCLK_150:
198 return 150000000;
199 case QIXIS_SYSCLK_160:
200 return 160000000;
201 case QIXIS_SYSCLK_166:
202 return 166666666;
203 }
204 #endif
205 return 100000000;
206 }
207
select_i2c_ch_pca9547(u8 ch)208 int select_i2c_ch_pca9547(u8 ch)
209 {
210 int ret;
211
212 #if !CONFIG_IS_ENABLED(DM_I2C)
213 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
214 #else
215 struct udevice *dev;
216
217 ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
218 if (!ret)
219 ret = dm_i2c_write(dev, 0, &ch, 1);
220 #endif
221
222 if (ret) {
223 puts("PCA: failed to select proper channel\n");
224 return ret;
225 }
226
227 return 0;
228 }
229
i2c_multiplexer_select_vid_channel(u8 channel)230 int i2c_multiplexer_select_vid_channel(u8 channel)
231 {
232 return select_i2c_ch_pca9547(channel);
233 }
234
config_board_mux(int ctrl_type)235 int config_board_mux(int ctrl_type)
236 {
237 #ifdef CONFIG_FSL_QIXIS
238 u8 reg5;
239
240 reg5 = QIXIS_READ(brdcfg[5]);
241
242 switch (ctrl_type) {
243 case MUX_TYPE_SDHC:
244 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
245 break;
246 case MUX_TYPE_DSPI:
247 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
248 break;
249 default:
250 printf("Wrong mux interface type\n");
251 return -1;
252 }
253
254 QIXIS_WRITE(brdcfg[5], reg5);
255 #endif
256 return 0;
257 }
258
board_init(void)259 int board_init(void)
260 {
261 #ifdef CONFIG_FSL_MC_ENET
262 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
263 #endif
264
265 init_final_memctl_regs();
266
267 #ifdef CONFIG_ENV_IS_NOWHERE
268 gd->env_addr = (ulong)&default_environment[0];
269 #endif
270 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
271
272 #ifdef CONFIG_FSL_QIXIS
273 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
274 #endif
275
276 #ifdef CONFIG_FSL_CAAM
277 sec_init();
278 #endif
279 #ifdef CONFIG_FSL_LS_PPA
280 ppa_init();
281 #endif
282
283 #ifdef CONFIG_FSL_MC_ENET
284 /* invert AQR405 IRQ pins polarity */
285 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
286 #endif
287 #ifdef CONFIG_FSL_CAAM
288 sec_init();
289 #endif
290
291 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
292 pci_init();
293 #endif
294
295 return 0;
296 }
297
board_early_init_f(void)298 int board_early_init_f(void)
299 {
300 #ifdef CONFIG_SYS_I2C_EARLY_INIT
301 i2c_early_init_f();
302 #endif
303 fsl_lsch3_early_init_f();
304 return 0;
305 }
306
misc_init_r(void)307 int misc_init_r(void)
308 {
309 char *env_hwconfig;
310 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
311 u32 val;
312 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
313 u32 svr = gur_in32(&gur->svr);
314
315 val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
316
317 env_hwconfig = env_get("hwconfig");
318
319 if (hwconfig_f("dspi", env_hwconfig) &&
320 DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
321 config_board_mux(MUX_TYPE_DSPI);
322 else
323 config_board_mux(MUX_TYPE_SDHC);
324
325 /*
326 * LS2081ARDB RevF board has smart voltage translator
327 * which needs to be programmed to enable high speed SD interface
328 * by setting GPIO4_10 output to zero
329 */
330 #ifdef CONFIG_TARGET_LS2081ARDB
331 out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
332 in_le32(GPIO4_GPDIR_ADDR)));
333 out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
334 in_le32(GPIO4_GPDAT_ADDR)));
335 #endif
336 if (hwconfig("sdhc"))
337 config_board_mux(MUX_TYPE_SDHC);
338
339 if (adjust_vdd(0))
340 printf("Warning: Adjusting core voltage failed.\n");
341 /*
342 * Default value of board env is based on filename which is
343 * ls2080ardb. Modify board env for other supported SoCs
344 */
345 if ((SVR_SOC_VER(svr) == SVR_LS2088A) ||
346 (SVR_SOC_VER(svr) == SVR_LS2048A))
347 env_set("board", "ls2088ardb");
348 else if ((SVR_SOC_VER(svr) == SVR_LS2081A) ||
349 (SVR_SOC_VER(svr) == SVR_LS2041A))
350 env_set("board", "ls2081ardb");
351
352 return 0;
353 }
354
detail_board_ddr_info(void)355 void detail_board_ddr_info(void)
356 {
357 puts("\nDDR ");
358 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
359 print_ddr_info(0);
360 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
361 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
362 puts("\nDP-DDR ");
363 print_size(gd->bd->bi_dram[2].size, "");
364 print_ddr_info(CONFIG_DP_DDR_CTRL);
365 }
366 #endif
367 }
368
369 #ifdef CONFIG_FSL_MC_ENET
fdt_fixup_board_enet(void * fdt)370 void fdt_fixup_board_enet(void *fdt)
371 {
372 int offset;
373
374 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
375
376 if (offset < 0)
377 offset = fdt_path_offset(fdt, "/fsl-mc");
378
379 if (offset < 0) {
380 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
381 __func__, offset);
382 return;
383 }
384
385 if (get_mc_boot_status() == 0 &&
386 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
387 fdt_status_okay(fdt, offset);
388 else
389 fdt_status_fail(fdt, offset);
390 }
391
board_quiesce_devices(void)392 void board_quiesce_devices(void)
393 {
394 fsl_mc_ldpaa_exit(gd->bd);
395 }
396 #endif
397
398 #ifdef CONFIG_OF_BOARD_SETUP
fsl_fdt_fixup_flash(void * fdt)399 void fsl_fdt_fixup_flash(void *fdt)
400 {
401 int offset;
402 #ifdef CONFIG_TFABOOT
403 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
404 u32 val;
405 #endif
406
407 /*
408 * IFC and QSPI are muxed on board.
409 * So disable IFC node in dts if QSPI is enabled or
410 * disable QSPI node in dts in case QSPI is not enabled.
411 */
412 #ifdef CONFIG_TFABOOT
413 enum boot_src src = get_boot_src();
414 bool disable_ifc = false;
415
416 switch (src) {
417 case BOOT_SOURCE_IFC_NOR:
418 disable_ifc = false;
419 break;
420 case BOOT_SOURCE_QSPI_NOR:
421 disable_ifc = true;
422 break;
423 default:
424 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
425 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
426 disable_ifc = true;
427 break;
428 }
429
430 if (disable_ifc) {
431 offset = fdt_path_offset(fdt, "/soc/ifc");
432
433 if (offset < 0)
434 offset = fdt_path_offset(fdt, "/ifc");
435 } else {
436 offset = fdt_path_offset(fdt, "/soc/quadspi");
437
438 if (offset < 0)
439 offset = fdt_path_offset(fdt, "/quadspi");
440 }
441
442 #else
443 #ifdef CONFIG_FSL_QSPI
444 offset = fdt_path_offset(fdt, "/soc/ifc");
445
446 if (offset < 0)
447 offset = fdt_path_offset(fdt, "/ifc");
448 #else
449 offset = fdt_path_offset(fdt, "/soc/quadspi");
450
451 if (offset < 0)
452 offset = fdt_path_offset(fdt, "/quadspi");
453 #endif
454 #endif
455
456 if (offset < 0)
457 return;
458
459 fdt_status_disabled(fdt, offset);
460 }
461
ft_board_setup(void * blob,struct bd_info * bd)462 int ft_board_setup(void *blob, struct bd_info *bd)
463 {
464 int i;
465 u16 mc_memory_bank = 0;
466
467 u64 *base;
468 u64 *size;
469 u64 mc_memory_base = 0;
470 u64 mc_memory_size = 0;
471 u16 total_memory_banks;
472
473 ft_cpu_setup(blob, bd);
474
475 fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
476
477 if (mc_memory_base != 0)
478 mc_memory_bank++;
479
480 total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
481
482 base = calloc(total_memory_banks, sizeof(u64));
483 size = calloc(total_memory_banks, sizeof(u64));
484
485 /* fixup DT for the two GPP DDR banks */
486 base[0] = gd->bd->bi_dram[0].start;
487 size[0] = gd->bd->bi_dram[0].size;
488 base[1] = gd->bd->bi_dram[1].start;
489 size[1] = gd->bd->bi_dram[1].size;
490
491 #ifdef CONFIG_RESV_RAM
492 /* reduce size if reserved memory is within this bank */
493 if (gd->arch.resv_ram >= base[0] &&
494 gd->arch.resv_ram < base[0] + size[0])
495 size[0] = gd->arch.resv_ram - base[0];
496 else if (gd->arch.resv_ram >= base[1] &&
497 gd->arch.resv_ram < base[1] + size[1])
498 size[1] = gd->arch.resv_ram - base[1];
499 #endif
500
501 if (mc_memory_base != 0) {
502 for (i = 0; i <= total_memory_banks; i++) {
503 if (base[i] == 0 && size[i] == 0) {
504 base[i] = mc_memory_base;
505 size[i] = mc_memory_size;
506 break;
507 }
508 }
509 }
510
511 fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
512
513 fdt_fsl_mc_fixup_iommu_map_entry(blob);
514
515 fsl_fdt_fixup_dr_usb(blob, bd);
516
517 fsl_fdt_fixup_flash(blob);
518
519 #ifdef CONFIG_FSL_MC_ENET
520 fdt_fixup_board_enet(blob);
521 #endif
522
523 fdt_fixup_icid(blob);
524
525 return 0;
526 }
527 #endif
528
qixis_dump_switch(void)529 void qixis_dump_switch(void)
530 {
531 #ifdef CONFIG_FSL_QIXIS
532 int i, nr_of_cfgsw;
533
534 QIXIS_WRITE(cms[0], 0x00);
535 nr_of_cfgsw = QIXIS_READ(cms[1]);
536
537 puts("DIP switch settings dump:\n");
538 for (i = 1; i <= nr_of_cfgsw; i++) {
539 QIXIS_WRITE(cms[0], i);
540 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
541 }
542 #endif
543 }
544
545 /*
546 * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
547 * Both slots has 0x54, resulting 2nd slot unusable.
548 */
update_spd_address(unsigned int ctrl_num,unsigned int slot,unsigned int * addr)549 void update_spd_address(unsigned int ctrl_num,
550 unsigned int slot,
551 unsigned int *addr)
552 {
553 #ifndef CONFIG_TARGET_LS2081ARDB
554 #ifdef CONFIG_FSL_QIXIS
555 u8 sw;
556
557 sw = QIXIS_READ(arch);
558 if ((sw & 0xf) < 0x3) {
559 if (ctrl_num == 1 && slot == 0)
560 *addr = SPD_EEPROM_ADDRESS4;
561 else if (ctrl_num == 1 && slot == 1)
562 *addr = SPD_EEPROM_ADDRESS3;
563 }
564 #endif
565 #endif
566 }
567