1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2010-2012 Freescale Semiconductor, Inc.
4 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
5 */
6
7 #include <common.h>
8 #include <init.h>
9 #include <spi.h>
10 #include <asm/global_data.h>
11 #include <asm/io.h>
12 #include <asm/immap.h>
13 #include <mmc.h>
14 #include <fsl_esdhc_imx.h>
15 #include <linux/delay.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
checkboard(void)19 int checkboard(void)
20 {
21 /*
22 * need to to:
23 * Check serial flash size. if 2mb evb, else 8mb demo
24 */
25 puts("Board: ");
26 puts("Freescale MCF54418 Tower System\n");
27 return 0;
28 };
29
dram_init(void)30 int dram_init(void)
31 {
32 u32 dramsize;
33
34 #if defined(CONFIG_SERIAL_BOOT)
35 /*
36 * Serial Boot: The dram is already initialized in start.S
37 * only require to return DRAM size
38 */
39 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
40 #else
41 sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
42 ccm_t *ccm = (ccm_t *)MMAP_CCM;
43 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
44 pm_t *pm = (pm_t *) MMAP_PM;
45 u32 i;
46
47 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
48
49 for (i = 0x13; i < 0x20; i++) {
50 if (dramsize == (1 << i))
51 break;
52 }
53
54 out_8(&pm->pmcr0, 0x2E);
55 out_8(&gpio->mscr_sdram, 1);
56
57 clrbits_be16(&ccm->misccr2, CCM_MISCCR2_FBHALF);
58 setbits_be16(&ccm->misccr2, CCM_MISCCR2_DDR2CLK);
59
60 out_be32(&sdram->rcrcr, 0x40000000);
61 out_be32(&sdram->padcr, 0x01030203);
62
63 out_be32(&sdram->cr00, 0x01010101);
64 out_be32(&sdram->cr01, 0x00000101);
65 out_be32(&sdram->cr02, 0x01010100);
66 out_be32(&sdram->cr03, 0x01010000);
67 out_be32(&sdram->cr04, 0x00010101);
68 out_be32(&sdram->cr06, 0x00010100);
69 out_be32(&sdram->cr07, 0x00000001);
70 out_be32(&sdram->cr08, 0x01000001);
71 out_be32(&sdram->cr09, 0x00000100);
72 out_be32(&sdram->cr10, 0x00010001);
73 out_be32(&sdram->cr11, 0x00000200);
74 out_be32(&sdram->cr12, 0x01000002);
75 out_be32(&sdram->cr13, 0x00000000);
76 out_be32(&sdram->cr14, 0x00000100);
77 out_be32(&sdram->cr15, 0x02000100);
78 out_be32(&sdram->cr16, 0x02000407);
79 out_be32(&sdram->cr17, 0x02030007);
80 out_be32(&sdram->cr18, 0x02000100);
81 out_be32(&sdram->cr19, 0x0A030203);
82 out_be32(&sdram->cr20, 0x00020708);
83 out_be32(&sdram->cr21, 0x00050008);
84 out_be32(&sdram->cr22, 0x04030002);
85 out_be32(&sdram->cr23, 0x00000004);
86 out_be32(&sdram->cr24, 0x020A0000);
87 out_be32(&sdram->cr25, 0x0C00000E);
88 out_be32(&sdram->cr26, 0x00002004);
89 out_be32(&sdram->cr28, 0x00100010);
90 out_be32(&sdram->cr29, 0x00100010);
91 out_be32(&sdram->cr31, 0x07990000);
92 out_be32(&sdram->cr40, 0x00000000);
93 out_be32(&sdram->cr41, 0x00C80064);
94 out_be32(&sdram->cr42, 0x44520002);
95 out_be32(&sdram->cr43, 0x00C80023);
96 out_be32(&sdram->cr45, 0x0000C350);
97 out_be32(&sdram->cr56, 0x04000000);
98 out_be32(&sdram->cr57, 0x03000304);
99 out_be32(&sdram->cr58, 0x40040000);
100 out_be32(&sdram->cr59, 0xC0004004);
101 out_be32(&sdram->cr60, 0x0642C000);
102 out_be32(&sdram->cr61, 0x00000642);
103 asm("tpf");
104
105 out_be32(&sdram->cr09, 0x01000100);
106
107 udelay(100);
108 #endif
109 gd->ram_size = dramsize;
110
111 return 0;
112 };
113
testdram(void)114 int testdram(void)
115 {
116 return 0;
117 }
118