1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2006
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 */
6
7 #include <common.h>
8 #include <fdt_support.h>
9 #include <init.h>
10 #include <ioports.h>
11 #include <mpc83xx.h>
12 #include <asm/bitops.h>
13 #include <asm/global_data.h>
14 #include <asm/mpc8349_pci.h>
15 #include <i2c.h>
16 #include <spi.h>
17 #include <miiphy.h>
18 #ifdef CONFIG_SYS_FSL_DDR2
19 #include <fsl_ddr_sdram.h>
20 #else
21 #include <spd_sdram.h>
22 #endif
23 #include <linux/delay.h>
24
25 #if defined(CONFIG_OF_LIBFDT)
26 #include <linux/libfdt.h>
27 #endif
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 int fixed_sdram(void);
32 void sdram_init(void);
33
34 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
35 void ddr_enable_ecc(unsigned int dram_size);
36 #endif
37
board_early_init_f(void)38 int board_early_init_f (void)
39 {
40 volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
41
42 /* Enable flash write */
43 bcsr[1] &= ~0x01;
44
45 #ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
46 /* Use USB PHY on SYS board */
47 bcsr[5] |= 0x02;
48 #endif
49
50 return 0;
51 }
52
53 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
54
dram_init(void)55 int dram_init(void)
56 {
57 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
58 phys_size_t msize = 0;
59
60 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
61 return -ENXIO;
62
63 /* DDR SDRAM - Main SODIMM */
64 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
65 #if defined(CONFIG_SPD_EEPROM)
66 #ifndef CONFIG_SYS_FSL_DDR2
67 msize = spd_sdram() * 1024 * 1024;
68 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
69 ddr_enable_ecc(msize);
70 #endif
71 #else
72 msize = fsl_ddr_sdram();
73 #endif
74 #else
75 msize = fixed_sdram() * 1024 * 1024;
76 #endif
77 /*
78 * Initialize SDRAM if it is on local bus.
79 */
80 sdram_init();
81
82 /* set total bus SDRAM size(bytes) -- DDR */
83 gd->ram_size = msize;
84
85 return 0;
86 }
87
88 #if !defined(CONFIG_SPD_EEPROM)
89 /*************************************************************************
90 * fixed sdram init -- doesn't use serial presence detect.
91 ************************************************************************/
fixed_sdram(void)92 int fixed_sdram(void)
93 {
94 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
95 u32 msize = CONFIG_SYS_DDR_SIZE;
96 u32 ddr_size = msize << 20; /* DDR size in bytes */
97 u32 ddr_size_log2 = __ilog2(ddr_size);
98
99 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
100 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
101
102 #if (CONFIG_SYS_DDR_SIZE != 256)
103 #warning Currenly any ddr size other than 256 is not supported
104 #endif
105 #ifdef CONFIG_DDR_II
106 im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
107 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
108 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
109 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
110 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
111 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
112 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
113 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
114 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
115 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
116 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
117 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
118 #else
119
120 #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
121 #warning Chip select bounds is only configurable in 16MB increments
122 #endif
123 im->ddr.csbnds[2].csbnds =
124 ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
125 (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
126 CSBNDS_EA_SHIFT) & CSBNDS_EA);
127 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
128
129 /* currently we use only one CS, so disable the other banks */
130 im->ddr.cs_config[0] = 0;
131 im->ddr.cs_config[1] = 0;
132 im->ddr.cs_config[3] = 0;
133
134 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
135 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
136
137 im->ddr.sdram_cfg =
138 SDRAM_CFG_SREN
139 #if defined(CONFIG_DDR_2T_TIMING)
140 | SDRAM_CFG_2T_EN
141 #endif
142 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
143 #if defined (CONFIG_DDR_32BIT)
144 /* for 32-bit mode burst length is 8 */
145 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
146 #endif
147 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
148
149 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
150 #endif
151 udelay(200);
152
153 /* enable DDR controller */
154 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
155 return msize;
156 }
157 #endif/*!CONFIG_SYS_SPD_EEPROM*/
158
159
checkboard(void)160 int checkboard (void)
161 {
162 /*
163 * Warning: do not read the BCSR registers here
164 *
165 * There is a timing bug in the 8349E and 8349EA BCSR code
166 * version 1.2 (read from BCSR 11) that will cause the CFI
167 * flash initialization code to overwrite BCSR 0, disabling
168 * the serial ports and gigabit ethernet
169 */
170
171 puts("Board: Freescale MPC8349EMDS\n");
172 return 0;
173 }
174
175 /*
176 * if MPC8349EMDS is soldered with SDRAM
177 */
178 #if defined(CONFIG_SYS_BR2_PRELIM) \
179 && defined(CONFIG_SYS_OR2_PRELIM) \
180 && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
181 && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
182 /*
183 * Initialize SDRAM memory on the Local Bus.
184 */
185
sdram_init(void)186 void sdram_init(void)
187 {
188 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
189 volatile fsl_lbc_t *lbc = &immap->im_lbc;
190 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
191 const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
192 LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
193 LSDMR_WRC3 | LSDMR_CL3;
194 /*
195 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
196 */
197
198 /* setup mtrpt, lsrt and lbcr for LB bus */
199 lbc->lbcr = 0x00000000;
200 /* LB refresh timer prescal, 266MHz/32 */
201 lbc->mrtpr = 0x20000000;
202 /* LB sdram refresh timer, about 6us */
203 lbc->lsrt = 0x32000000;
204 asm("sync");
205
206 /*
207 * Configure the SDRAM controller Machine Mode Register.
208 */
209
210 /* 0x40636733; normal operation */
211 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
212
213 /* 0x68636733; precharge all the banks */
214 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
215 asm("sync");
216 *sdram_addr = 0xff;
217 udelay(100);
218
219 /* 0x48636733; auto refresh */
220 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
221 asm("sync");
222 /*1 times*/
223 *sdram_addr = 0xff;
224 udelay(100);
225 /*2 times*/
226 *sdram_addr = 0xff;
227 udelay(100);
228 /*3 times*/
229 *sdram_addr = 0xff;
230 udelay(100);
231 /*4 times*/
232 *sdram_addr = 0xff;
233 udelay(100);
234 /*5 times*/
235 *sdram_addr = 0xff;
236 udelay(100);
237 /*6 times*/
238 *sdram_addr = 0xff;
239 udelay(100);
240 /*7 times*/
241 *sdram_addr = 0xff;
242 udelay(100);
243 /*8 times*/
244 *sdram_addr = 0xff;
245 udelay(100);
246
247 /* 0x58636733; mode register write operation */
248 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
249 asm("sync");
250 *sdram_addr = 0xff;
251 udelay(100);
252
253 /* 0x40636733; normal operation */
254 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
255 asm("sync");
256 *sdram_addr = 0xff;
257 udelay(100);
258 }
259 #else
sdram_init(void)260 void sdram_init(void)
261 {
262 }
263 #endif
264
265 /*
266 * The following are used to control the SPI chip selects for the SPI command.
267 */
268 #ifdef CONFIG_MPC8XXX_SPI
269
270 #define SPI_CS_MASK 0x80000000
271
spi_cs_is_valid(unsigned int bus,unsigned int cs)272 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
273 {
274 return bus == 0 && cs == 0;
275 }
276
spi_cs_activate(struct spi_slave * slave)277 void spi_cs_activate(struct spi_slave *slave)
278 {
279 volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
280
281 iopd->dat &= ~SPI_CS_MASK;
282 }
283
spi_cs_deactivate(struct spi_slave * slave)284 void spi_cs_deactivate(struct spi_slave *slave)
285 {
286 volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
287
288 iopd->dat |= SPI_CS_MASK;
289 }
290 #endif
291
292 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,struct bd_info * bd)293 int ft_board_setup(void *blob, struct bd_info *bd)
294 {
295 ft_cpu_setup(blob, bd);
296 #ifdef CONFIG_PCI
297 ft_pci_setup(blob, bd);
298 #endif
299
300 return 0;
301 }
302 #endif
303