1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <init.h>
8 #include <linux/delay.h>
9
10 #include <asm/mmu.h>
11 #include <asm/io.h>
12 #include <mpc83xx.h>
13 #include <pci.h>
14 #include <i2c.h>
15 #include <asm/fsl_i2c.h>
16
17 static struct pci_region pci1_regions[] = {
18 {
19 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
20 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
21 size: CONFIG_SYS_PCI1_MEM_SIZE,
22 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
23 },
24 {
25 bus_start: CONFIG_SYS_PCI1_IO_BASE,
26 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
27 size: CONFIG_SYS_PCI1_IO_SIZE,
28 flags: PCI_REGION_IO
29 },
30 {
31 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
32 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
33 size: CONFIG_SYS_PCI1_MMIO_SIZE,
34 flags: PCI_REGION_MEM
35 },
36 };
37
38 #ifdef CONFIG_MPC83XX_PCI2
39 static struct pci_region pci2_regions[] = {
40 {
41 bus_start: CONFIG_SYS_PCI2_MEM_BASE,
42 phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
43 size: CONFIG_SYS_PCI2_MEM_SIZE,
44 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
45 },
46 {
47 bus_start: CONFIG_SYS_PCI2_IO_BASE,
48 phys_start: CONFIG_SYS_PCI2_IO_PHYS,
49 size: CONFIG_SYS_PCI2_IO_SIZE,
50 flags: PCI_REGION_IO
51 },
52 {
53 bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
54 phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
55 size: CONFIG_SYS_PCI2_MMIO_SIZE,
56 flags: PCI_REGION_MEM
57 },
58 };
59 #endif
60
pci_init_board(void)61 void pci_init_board(void)
62 {
63 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
64 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
65 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
66 #ifndef CONFIG_MPC83XX_PCI2
67 struct pci_region *reg[] = { pci1_regions };
68 #else
69 struct pci_region *reg[] = { pci1_regions, pci2_regions };
70 #endif
71 u8 reg8;
72
73 #if defined(CONFIG_SYS_I2C)
74 i2c_set_bus_num(1);
75 /* Read the PCI_M66EN jumper setting */
76 if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) ||
77 (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) {
78 if (reg8 & I2C_8574_PCI66)
79 clk->occr = 0xff000000; /* 66 MHz PCI */
80 else
81 clk->occr = 0xff600001; /* 33 MHz PCI */
82 } else {
83 clk->occr = 0xff600001; /* 33 MHz PCI */
84 }
85 #else
86 clk->occr = 0xff000000; /* 66 MHz PCI */
87 #endif
88 udelay(2000);
89
90 /* Configure PCI Local Access Windows */
91 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
92 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
93
94 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
95 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
96
97 udelay(2000);
98
99 #ifndef CONFIG_MPC83XX_PCI2
100 mpc83xx_pci_init(1, reg);
101 #else
102 mpc83xx_pci_init(2, reg);
103 #endif
104 }
105