1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2007,2010 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
5 */
6
7 #include <common.h>
8 #include <hwconfig.h>
9 #include <i2c.h>
10 #include <init.h>
11 #include <net.h>
12 #include <asm/bitops.h>
13 #include <asm/global_data.h>
14 #include <asm/io.h>
15 #include <asm/fsl_mpc83xx_serdes.h>
16 #include <spd_sdram.h>
17 #include <tsec.h>
18 #include <linux/delay.h>
19 #include <linux/libfdt.h>
20 #include <fdt_support.h>
21 #include <fsl_esdhc.h>
22 #include <fsl_mdio.h>
23 #include <phy.h>
24 #include "pci.h"
25 #include "../common/pq-mds-pib.h"
26
27 DECLARE_GLOBAL_DATA_PTR;
28
board_early_init_f(void)29 int board_early_init_f(void)
30 {
31 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
32
33 /* Enable flash write */
34 bcsr[0x9] &= ~0x04;
35 /* Clear all of the interrupt of BCSR */
36 bcsr[0xe] = 0xff;
37
38 #ifdef CONFIG_FSL_SERDES
39 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
40 u32 spridr = in_be32(&immr->sysconf.spridr);
41
42 /* we check only part num, and don't look for CPU revisions */
43 switch (PARTID_NO_E(spridr)) {
44 case SPR_8377:
45 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
46 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
47 break;
48 case SPR_8378:
49 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII,
50 FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V);
51 break;
52 case SPR_8379:
53 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
54 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
55 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
56 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
57 break;
58 default:
59 printf("serdes not configured: unknown CPU part number: "
60 "%04x\n", spridr >> 16);
61 break;
62 }
63 #endif /* CONFIG_FSL_SERDES */
64 return 0;
65 }
66
67 #ifdef CONFIG_FSL_ESDHC
board_mmc_init(struct bd_info * bd)68 int board_mmc_init(struct bd_info *bd)
69 {
70 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
71 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
72
73 if (!hwconfig("esdhc"))
74 return 0;
75
76 /* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */
77 bcsr[0xc] |= 0x4c;
78
79 /* Set proper bits in SICR to allow SD signals through */
80 clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
81 clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI,
82 SICRH_GPIO2_E_SD | SICRH_SPI_SD);
83
84 return fsl_esdhc_mmc_init(bd);
85 }
86 #endif
87
88 #if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2)
board_eth_init(struct bd_info * bd)89 int board_eth_init(struct bd_info *bd)
90 {
91 struct fsl_pq_mdio_info mdio_info;
92 struct tsec_info_struct tsec_info[2];
93 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
94 u32 rcwh = in_be32(&im->reset.rcwh);
95 u32 tsec_mode;
96 int num = 0;
97
98 /* New line after Net: */
99 printf("\n");
100
101 #ifdef CONFIG_TSEC1
102 SET_STD_TSEC_INFO(tsec_info[num], 1);
103
104 printf(CONFIG_TSEC1_NAME ": ");
105
106 tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
107 if (tsec_mode == HRCWH_TSEC1M_IN_RGMII) {
108 printf("RGMII\n");
109 /* this is default, no need to fixup */
110 } else if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) {
111 printf("SGMII\n");
112 tsec_info[num].phyaddr = TSEC1_PHY_ADDR_SGMII;
113 tsec_info[num].flags = TSEC_GIGABIT;
114 } else {
115 printf("unsupported PHY type\n");
116 }
117 num++;
118 #endif
119 #ifdef CONFIG_TSEC2
120 SET_STD_TSEC_INFO(tsec_info[num], 2);
121
122 printf(CONFIG_TSEC2_NAME ": ");
123
124 tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
125 if (tsec_mode == HRCWH_TSEC2M_IN_RGMII) {
126 printf("RGMII\n");
127 /* this is default, no need to fixup */
128 } else if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) {
129 printf("SGMII\n");
130 tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
131 tsec_info[num].flags = TSEC_GIGABIT;
132 } else {
133 printf("unsupported PHY type\n");
134 }
135 num++;
136 #endif
137
138 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
139 mdio_info.name = DEFAULT_MII_NAME;
140 fsl_pq_mdio_init(bd, &mdio_info);
141
142 return tsec_eth_init(bd, tsec_info, num);
143 }
144
__ft_tsec_fixup(void * blob,struct bd_info * bd,const char * alias,int phy_addr)145 static void __ft_tsec_fixup(void *blob, struct bd_info *bd, const char *alias,
146 int phy_addr)
147 {
148 const u32 *ph;
149 int off;
150 int err;
151
152 off = fdt_path_offset(blob, alias);
153 if (off < 0) {
154 printf("WARNING: could not find %s alias: %s.\n", alias,
155 fdt_strerror(off));
156 return;
157 }
158
159 err = fdt_fixup_phy_connection(blob, off, PHY_INTERFACE_MODE_SGMII);
160
161 if (err) {
162 printf("WARNING: could not set phy-connection-type for %s: "
163 "%s.\n", alias, fdt_strerror(err));
164 return;
165 }
166
167 ph = (u32 *)fdt_getprop(blob, off, "phy-handle", 0);
168 if (!ph) {
169 printf("WARNING: could not get phy-handle for %s.\n",
170 alias);
171 return;
172 }
173
174 off = fdt_node_offset_by_phandle(blob, *ph);
175 if (off < 0) {
176 printf("WARNING: could not get phy node for %s: %s\n", alias,
177 fdt_strerror(off));
178 return;
179 }
180
181 phy_addr = cpu_to_fdt32(phy_addr);
182 err = fdt_setprop(blob, off, "reg", &phy_addr, sizeof(phy_addr));
183 if (err < 0) {
184 printf("WARNING: could not set phy node's reg for %s: "
185 "%s.\n", alias, fdt_strerror(err));
186 return;
187 }
188 }
189
ft_tsec_fixup(void * blob,struct bd_info * bd)190 static void ft_tsec_fixup(void *blob, struct bd_info *bd)
191 {
192 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
193 u32 rcwh = in_be32(&im->reset.rcwh);
194 u32 tsec_mode;
195
196 #ifdef CONFIG_TSEC1
197 tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
198 if (tsec_mode == HRCWH_TSEC1M_IN_SGMII)
199 __ft_tsec_fixup(blob, bd, "ethernet0", TSEC1_PHY_ADDR_SGMII);
200 #endif
201
202 #ifdef CONFIG_TSEC2
203 tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
204 if (tsec_mode == HRCWH_TSEC2M_IN_SGMII)
205 __ft_tsec_fixup(blob, bd, "ethernet1", TSEC2_PHY_ADDR_SGMII);
206 #endif
207 }
208 #else
ft_tsec_fixup(void * blob,struct bd_info * bd)209 static inline void ft_tsec_fixup(void *blob, struct bd_info *bd) {}
210 #endif /* defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) */
211
board_early_init_r(void)212 int board_early_init_r(void)
213 {
214 #ifdef CONFIG_PQ_MDS_PIB
215 pib_init();
216 #endif
217 return 0;
218 }
219
220 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
221 extern void ddr_enable_ecc(unsigned int dram_size);
222 #endif
223 int fixed_sdram(void);
224
dram_init(void)225 int dram_init(void)
226 {
227 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
228 u32 msize = 0;
229
230 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
231 return -ENXIO;
232
233 #if defined(CONFIG_SPD_EEPROM)
234 msize = spd_sdram();
235 #else
236 msize = fixed_sdram();
237 #endif
238
239 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
240 /* Initialize DDR ECC byte */
241 ddr_enable_ecc(msize * 1024 * 1024);
242 #endif
243
244 /* return total bus DDR size(bytes) */
245 gd->ram_size = msize * 1024 * 1024;
246
247 return 0;
248 }
249
250 #if !defined(CONFIG_SPD_EEPROM)
251 /*************************************************************************
252 * fixed sdram init -- doesn't use serial presence detect.
253 ************************************************************************/
fixed_sdram(void)254 int fixed_sdram(void)
255 {
256 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
257 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
258 u32 msize_log2 = __ilog2(msize);
259
260 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
261 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
262
263 #if (CONFIG_SYS_DDR_SIZE != 512)
264 #warning Currenly any ddr size other than 512 is not supported
265 #endif
266 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
267 udelay(50000);
268
269 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
270 udelay(1000);
271
272 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
273 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
274 udelay(1000);
275
276 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
277 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
278 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
279 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
280 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
281 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
282 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
283 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
284 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
285 __asm__ __volatile__("sync");
286 udelay(1000);
287
288 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
289 udelay(2000);
290 return CONFIG_SYS_DDR_SIZE;
291 }
292 #endif /*!CONFIG_SYS_SPD_EEPROM */
293
checkboard(void)294 int checkboard(void)
295 {
296 puts("Board: Freescale MPC837xEMDS\n");
297 return 0;
298 }
299
300 #ifdef CONFIG_PCI
board_pci_host_broken(void)301 int board_pci_host_broken(void)
302 {
303 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
304 const u32 rcw_mask = HRCWH_PCI1_ARBITER_ENABLE | HRCWH_PCI_HOST;
305
306 /* It's always OK in case of external arbiter. */
307 if (hwconfig_subarg_cmp("pci", "arbiter", "external"))
308 return 0;
309
310 if ((in_be32(&im->reset.rcwh) & rcw_mask) != rcw_mask)
311 return 1;
312
313 return 0;
314 }
315
ft_pci_fixup(void * blob,struct bd_info * bd)316 static void ft_pci_fixup(void *blob, struct bd_info *bd)
317 {
318 const char *status = "broken (no arbiter)";
319 int off;
320 int err;
321
322 off = fdt_path_offset(blob, "pci0");
323 if (off < 0) {
324 printf("WARNING: could not find pci0 alias: %s.\n",
325 fdt_strerror(off));
326 return;
327 }
328
329 err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
330 if (err) {
331 printf("WARNING: could not set status for pci0: %s.\n",
332 fdt_strerror(err));
333 return;
334 }
335 }
336 #endif
337
338 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,struct bd_info * bd)339 int ft_board_setup(void *blob, struct bd_info *bd)
340 {
341 ft_cpu_setup(blob, bd);
342 ft_tsec_fixup(blob, bd);
343 fsl_fdt_fixup_dr_usb(blob, bd);
344 fdt_fixup_esdhc(blob, bd);
345 #ifdef CONFIG_PCI
346 ft_pci_setup(blob, bd);
347 if (board_pci_host_broken())
348 ft_pci_fixup(blob, bd);
349 ft_pcie_fixup(blob, bd);
350 #endif
351
352 return 0;
353 }
354 #endif /* CONFIG_OF_BOARD_SETUP */
355