1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2004, 2007, 2009-2011 Freescale Semiconductor, Inc.
4 *
5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 */
7
8 #include <common.h>
9 #include <init.h>
10 #include <net.h>
11 #include <pci.h>
12 #include <vsprintf.h>
13 #include <asm/processor.h>
14 #include <asm/mmu.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_pci.h>
17 #include <fsl_ddr_sdram.h>
18 #include <asm/fsl_serdes.h>
19 #include <miiphy.h>
20 #include <linux/delay.h>
21 #include <linux/libfdt.h>
22 #include <fdt_support.h>
23 #include <tsec.h>
24 #include <fsl_mdio.h>
25 #include <netdev.h>
26
27 #include "../common/cadmus.h"
28 #include "../common/eeprom.h"
29 #include "../common/via.h"
30
31 void local_bus_init(void);
32
checkboard(void)33 int checkboard (void)
34 {
35 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
36 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
37
38 /* PCI slot in USER bits CSR[6:7] by convention. */
39 uint pci_slot = get_pci_slot ();
40
41 uint cpu_board_rev = get_cpu_board_revision ();
42
43 puts("Board: MPC8548CDS");
44 printf(" Carrier Rev: 0x%02x, PCI Slot %d\n",
45 get_board_version(), pci_slot);
46 printf(" Daughtercard Rev: %d.%d (0x%04x)\n",
47 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
48 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
49 /*
50 * Initialize local bus.
51 */
52 local_bus_init ();
53
54 /*
55 * Hack TSEC 3 and 4 IO voltages.
56 */
57 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
58
59 ecm->eedr = 0xffffffff; /* clear ecm errors */
60 ecm->eeer = 0xffffffff; /* enable ecm errors */
61 return 0;
62 }
63
64 /*
65 * Initialize Local Bus
66 */
67 void
local_bus_init(void)68 local_bus_init(void)
69 {
70 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
71 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
72
73 uint clkdiv;
74 sys_info_t sysinfo;
75
76 get_sys_info(&sysinfo);
77 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
78
79 gur->lbiuiplldcr1 = 0x00078080;
80 if (clkdiv == 16) {
81 gur->lbiuiplldcr0 = 0x7c0f1bf0;
82 } else if (clkdiv == 8) {
83 gur->lbiuiplldcr0 = 0x6c0f1bf0;
84 } else if (clkdiv == 4) {
85 gur->lbiuiplldcr0 = 0x5c0f1bf0;
86 }
87
88 lbc->lcrr |= 0x00030000;
89
90 asm("sync;isync;msync");
91
92 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
93 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
94 }
95
96 /*
97 * Initialize SDRAM memory on the Local Bus.
98 */
lbc_sdram_init(void)99 void lbc_sdram_init(void)
100 {
101 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
102
103 uint idx;
104 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
105 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
106 uint lsdmr_common;
107
108 puts("LBC SDRAM: ");
109 print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
110 "\n");
111
112 /*
113 * Setup SDRAM Base and Option Registers
114 */
115 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
116 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
117 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
118 asm("msync");
119
120 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
121 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
122 asm("msync");
123
124 /*
125 * MPC8548 uses "new" 15-16 style addressing.
126 */
127 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
128 lsdmr_common |= LSDMR_BSMA1516;
129
130 /*
131 * Issue PRECHARGE ALL command.
132 */
133 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
134 asm("sync;msync");
135 *sdram_addr = 0xff;
136 ppcDcbf((unsigned long) sdram_addr);
137 udelay(100);
138
139 /*
140 * Issue 8 AUTO REFRESH commands.
141 */
142 for (idx = 0; idx < 8; idx++) {
143 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
144 asm("sync;msync");
145 *sdram_addr = 0xff;
146 ppcDcbf((unsigned long) sdram_addr);
147 udelay(100);
148 }
149
150 /*
151 * Issue 8 MODE-set command.
152 */
153 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
154 asm("sync;msync");
155 *sdram_addr = 0xff;
156 ppcDcbf((unsigned long) sdram_addr);
157 udelay(100);
158
159 /*
160 * Issue NORMAL OP command.
161 */
162 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
163 asm("sync;msync");
164 *sdram_addr = 0xff;
165 ppcDcbf((unsigned long) sdram_addr);
166 udelay(200); /* Overkill. Must wait > 200 bus cycles */
167
168 #endif /* enable SDRAM init */
169 }
170
171 #if (defined(CONFIG_PCI) || defined(CONFIG_PCI1)) && !defined(CONFIG_DM_PCI)
172 /* For some reason the Tundra PCI bridge shows up on itself as a
173 * different device. Work around that by refusing to configure it.
174 */
dummy_func(struct pci_controller * hose,pci_dev_t dev,struct pci_config_table * tab)175 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
176
177 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
178 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
179 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
180 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
181 mpc85xx_config_via_usbide, {0,0,0}},
182 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
183 mpc85xx_config_via_usb, {0,0,0}},
184 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
185 mpc85xx_config_via_usb2, {0,0,0}},
186 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
187 mpc85xx_config_via_power, {0,0,0}},
188 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
189 mpc85xx_config_via_ac97, {0,0,0}},
190 {},
191 };
192
193 static struct pci_controller pci1_hose;
194 #endif /* CONFIG_PCI */
195
196 #if !defined(CONFIG_DM_PCI)
pci_init_board(void)197 void pci_init_board(void)
198 {
199 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
200 struct fsl_pci_info pci_info;
201 u32 devdisr, pordevsr, io_sel;
202 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
203 int first_free_busno = 0;
204 char buf[32];
205
206 devdisr = in_be32(&gur->devdisr);
207 pordevsr = in_be32(&gur->pordevsr);
208 porpllsr = in_be32(&gur->porpllsr);
209 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
210
211 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
212
213 #ifdef CONFIG_PCI1
214 pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
215 pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
216 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
217 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
218
219 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
220 SET_STD_PCI_INFO(pci_info, 1);
221 set_next_law(pci_info.mem_phys,
222 law_size_bits(pci_info.mem_size), pci_info.law);
223 set_next_law(pci_info.io_phys,
224 law_size_bits(pci_info.io_size), pci_info.law);
225
226 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
227 printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
228 (pci_32) ? 32 : 64,
229 strmhz(buf, pci_speed),
230 pci_clk_sel ? "sync" : "async",
231 pci_agent ? "agent" : "host",
232 pci_arb ? "arbiter" : "external-arbiter",
233 pci_info.regs);
234
235 pci1_hose.config_table = pci_mpc85xxcds_config_table;
236 first_free_busno = fsl_pci_init_port(&pci_info,
237 &pci1_hose, first_free_busno);
238
239 #ifdef CONFIG_PCIX_CHECK
240 if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) {
241 /* PCI-X init */
242 if (CONFIG_SYS_CLK_FREQ < 66000000)
243 printf("PCI-X will only work at 66 MHz\n");
244
245 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
246 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
247 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
248 }
249 #endif
250 } else {
251 printf("PCI1: disabled\n");
252 }
253
254 puts("\n");
255 #else
256 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
257 #endif
258
259 #ifdef CONFIG_PCI2
260 {
261 uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */
262 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
263 if (pci_dual) {
264 printf("PCI2: 32 bit, 66 MHz, %s\n",
265 pci2_clk_sel ? "sync" : "async");
266 } else {
267 printf("PCI2: disabled\n");
268 }
269 }
270 #else
271 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
272 #endif /* CONFIG_PCI2 */
273
274 fsl_pcie_init_board(first_free_busno);
275 }
276 #endif
277
configure_rgmii(void)278 void configure_rgmii(void)
279 {
280 unsigned short temp;
281
282 /* Change the resistors for the PHY */
283 /* This is needed to get the RGMII working for the 1.3+
284 * CDS cards */
285 if (get_board_version() == 0x13) {
286 miiphy_write(DEFAULT_MII_NAME,
287 TSEC1_PHY_ADDR, 29, 18);
288
289 miiphy_read(DEFAULT_MII_NAME,
290 TSEC1_PHY_ADDR, 30, &temp);
291
292 temp = (temp & 0xf03f);
293 temp |= 2 << 9; /* 36 ohm */
294 temp |= 2 << 6; /* 39 ohm */
295
296 miiphy_write(DEFAULT_MII_NAME,
297 TSEC1_PHY_ADDR, 30, temp);
298
299 miiphy_write(DEFAULT_MII_NAME,
300 TSEC1_PHY_ADDR, 29, 3);
301
302 miiphy_write(DEFAULT_MII_NAME,
303 TSEC1_PHY_ADDR, 30, 0x8000);
304 }
305
306 return;
307 }
308
board_eth_init(struct bd_info * bis)309 int board_eth_init(struct bd_info *bis)
310 {
311 #ifdef CONFIG_TSEC_ENET
312 struct fsl_pq_mdio_info mdio_info;
313 struct tsec_info_struct tsec_info[4];
314 int num = 0;
315
316 #ifdef CONFIG_TSEC1
317 SET_STD_TSEC_INFO(tsec_info[num], 1);
318 num++;
319 #endif
320 #ifdef CONFIG_TSEC2
321 SET_STD_TSEC_INFO(tsec_info[num], 2);
322 num++;
323 #endif
324 #ifdef CONFIG_TSEC3
325 /* initialize TSEC3 only if Carrier is 1.3 or above on CDS */
326 if (get_board_version() >= 0x13) {
327 SET_STD_TSEC_INFO(tsec_info[num], 3);
328 tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
329 num++;
330 }
331 #endif
332 #ifdef CONFIG_TSEC4
333 /* initialize TSEC4 only if Carrier is 1.3 or above on CDS */
334 if (get_board_version() >= 0x13) {
335 SET_STD_TSEC_INFO(tsec_info[num], 4);
336 tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
337 num++;
338 }
339 #endif
340
341 if (!num) {
342 printf("No TSECs initialized\n");
343
344 return 0;
345 }
346
347 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
348 mdio_info.name = DEFAULT_MII_NAME;
349 fsl_pq_mdio_init(bis, &mdio_info);
350
351 tsec_eth_init(bis, tsec_info, num);
352 configure_rgmii();
353 #endif
354
355 return pci_eth_init(bis);
356 }
357
358 #if defined(CONFIG_OF_BOARD_SETUP) && !defined(CONFIG_DM_PCI)
ft_pci_setup(void * blob,struct bd_info * bd)359 void ft_pci_setup(void *blob, struct bd_info *bd)
360 {
361 FT_FSL_PCI_SETUP;
362 }
363 #endif
364