1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2010 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <init.h>
8 #include <asm/global_data.h>
9 #include <asm/io.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/iomux-mx53.h>
15 #include <linux/errno.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <netdev.h>
18 #include <i2c.h>
19 #include <mmc.h>
20 #include <fsl_esdhc_imx.h>
21 #include <power/pmic.h>
22 #include <fsl_pmic.h>
23 #include <asm/gpio.h>
24 #include <mc13892.h>
25
26 DECLARE_GLOBAL_DATA_PTR;
27
dram_init(void)28 int dram_init(void)
29 {
30 /* dram_init must store complete ramsize in gd->ram_size */
31 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
32 PHYS_SDRAM_1_SIZE);
33 return 0;
34 }
35
36 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
37 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
38
setup_iomux_uart(void)39 static void setup_iomux_uart(void)
40 {
41 static const iomux_v3_cfg_t uart_pads[] = {
42 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
43 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
44 };
45
46 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
47 }
48
49 #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
50 PAD_CTL_HYS | PAD_CTL_ODE)
51
setup_i2c(unsigned int port_number)52 static void setup_i2c(unsigned int port_number)
53 {
54 static const iomux_v3_cfg_t i2c1_pads[] = {
55 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
56 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
57 };
58
59 static const iomux_v3_cfg_t i2c2_pads[] = {
60 NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__I2C2_SDA, I2C_PAD_CTRL),
61 NEW_PAD_CTRL(MX53_PAD_KEY_COL3__I2C2_SCL, I2C_PAD_CTRL),
62 };
63
64 switch (port_number) {
65 case 0:
66 imx_iomux_v3_setup_multiple_pads(i2c1_pads,
67 ARRAY_SIZE(i2c1_pads));
68 break;
69 case 1:
70 imx_iomux_v3_setup_multiple_pads(i2c2_pads,
71 ARRAY_SIZE(i2c2_pads));
72 break;
73 default:
74 printf("Warning: Wrong I2C port number\n");
75 break;
76 }
77 }
78
power_init(void)79 void power_init(void)
80 {
81 unsigned int val;
82 struct pmic *p;
83 int ret;
84
85 ret = pmic_init(I2C_0);
86 if (ret)
87 return;
88
89 p = pmic_get("FSL_PMIC");
90 if (!p)
91 return;
92
93 /* Set VDDA to 1.25V */
94 pmic_reg_read(p, REG_SW_2, &val);
95 val &= ~SWX_OUT_MASK;
96 val |= SWX_OUT_1_25;
97 pmic_reg_write(p, REG_SW_2, val);
98
99 /*
100 * Need increase VCC and VDDA to 1.3V
101 * according to MX53 IC TO2 datasheet.
102 */
103 if (is_soc_rev(CHIP_REV_2_0) == 0) {
104 /* Set VCC to 1.3V for TO2 */
105 pmic_reg_read(p, REG_SW_1, &val);
106 val &= ~SWX_OUT_MASK;
107 val |= SWX_OUT_1_30;
108 pmic_reg_write(p, REG_SW_1, val);
109
110 /* Set VDDA to 1.3V for TO2 */
111 pmic_reg_read(p, REG_SW_2, &val);
112 val &= ~SWX_OUT_MASK;
113 val |= SWX_OUT_1_30;
114 pmic_reg_write(p, REG_SW_2, val);
115 }
116 }
117
setup_iomux_fec(void)118 static void setup_iomux_fec(void)
119 {
120 static const iomux_v3_cfg_t fec_pads[] = {
121 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
122 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
123 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
124 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
125 PAD_CTL_HYS | PAD_CTL_PKE),
126 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
127 PAD_CTL_HYS | PAD_CTL_PKE),
128 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
129 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
130 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
131 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
132 PAD_CTL_HYS | PAD_CTL_PKE),
133 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
134 PAD_CTL_HYS | PAD_CTL_PKE),
135 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
136 PAD_CTL_HYS | PAD_CTL_PKE),
137 };
138
139 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
140 }
141
142 #ifdef CONFIG_FSL_ESDHC_IMX
143 struct fsl_esdhc_cfg esdhc_cfg[2] = {
144 {MMC_SDHC1_BASE_ADDR},
145 {MMC_SDHC3_BASE_ADDR},
146 };
147
board_mmc_getcd(struct mmc * mmc)148 int board_mmc_getcd(struct mmc *mmc)
149 {
150 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
151 int ret;
152
153 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
154 gpio_direction_input(IMX_GPIO_NR(3, 11));
155 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
156 gpio_direction_input(IMX_GPIO_NR(3, 13));
157
158 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
159 ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
160 else
161 ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
162
163 return ret;
164 }
165
166 #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
167 PAD_CTL_PUS_100K_UP)
168 #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
169 PAD_CTL_DSE_HIGH)
170
board_mmc_init(struct bd_info * bis)171 int board_mmc_init(struct bd_info *bis)
172 {
173 static const iomux_v3_cfg_t sd1_pads[] = {
174 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
175 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
176 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
177 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
178 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
179 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
180 MX53_PAD_EIM_DA13__GPIO3_13,
181 };
182
183 static const iomux_v3_cfg_t sd2_pads[] = {
184 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
185 SD_CMD_PAD_CTRL),
186 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
187 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
188 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
189 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
190 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
191 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
192 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
193 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
194 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
195 MX53_PAD_EIM_DA11__GPIO3_11,
196 };
197
198 u32 index;
199 int ret;
200
201 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
202 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
203
204 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
205 switch (index) {
206 case 0:
207 imx_iomux_v3_setup_multiple_pads(sd1_pads,
208 ARRAY_SIZE(sd1_pads));
209 break;
210 case 1:
211 imx_iomux_v3_setup_multiple_pads(sd2_pads,
212 ARRAY_SIZE(sd2_pads));
213 break;
214 default:
215 printf("Warning: you configured more ESDHC controller"
216 "(%d) as supported by the board(2)\n",
217 CONFIG_SYS_FSL_ESDHC_NUM);
218 return -EINVAL;
219 }
220 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
221 if (ret)
222 return ret;
223 }
224
225 return 0;
226 }
227 #endif
228
board_early_init_f(void)229 int board_early_init_f(void)
230 {
231 setup_iomux_uart();
232 setup_iomux_fec();
233
234 return 0;
235 }
236
board_init(void)237 int board_init(void)
238 {
239 /* address of boot parameters */
240 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
241
242 return 0;
243 }
244
245 #ifdef CONFIG_CMD_BMODE
246 static const struct boot_mode board_boot_modes[] = {
247 /* 4 bit bus width */
248 {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
249 {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
250 {NULL, 0},
251 };
252 #endif
253
board_late_init(void)254 int board_late_init(void)
255 {
256 setup_i2c(1);
257 power_init();
258
259 #ifdef CONFIG_CMD_BMODE
260 add_board_boot_modes(board_boot_modes);
261 #endif
262 return 0;
263 }
264
checkboard(void)265 int checkboard(void)
266 {
267 puts("Board: MX53EVK\n");
268
269 return 0;
270 }
271