1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <init.h>
8 #include <net.h>
9 #include <asm/global_data.h>
10 #include <asm/io.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/clock.h>
14 #include <linux/errno.h>
15 #include <asm/gpio.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <mmc.h>
18 #include <fsl_esdhc_imx.h>
19 #include <miiphy.h>
20 #include <netdev.h>
21 #include <usb.h>
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
26 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
27 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
28
29 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
30 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
31 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
32
33 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
34 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
35
dram_init(void)36 int dram_init(void)
37 {
38 #if defined(CONFIG_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \
39 defined(CONFIG_DDR_32BIT)
40 gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024) / 2;
41 #else
42 gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
43 #endif
44
45 return 0;
46 }
47
48 iomux_v3_cfg_t const uart4_pads[] = {
49 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
50 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
51 };
52
53 iomux_v3_cfg_t const usdhc3_pads[] = {
54 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
55 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
56 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
57 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
58 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
59 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
60 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
61 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
62 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
63 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
64 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
65 };
66
67 iomux_v3_cfg_t const usdhc4_pads[] = {
68 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
69 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
70 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
71 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
72 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
73 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
74 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
75 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
76 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
77 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
78 };
79
80 iomux_v3_cfg_t const enet_pads[] = {
81 MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
83 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
84 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
85 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
86 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
87 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
88 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
89 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
90 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
91 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
92 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
93 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
94 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
95 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
96 };
97
98
setup_iomux_uart(void)99 static void setup_iomux_uart(void)
100 {
101 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
102 }
103
setup_iomux_enet(void)104 static void setup_iomux_enet(void)
105 {
106 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
107 }
108
109 #ifdef CONFIG_FSL_ESDHC_IMX
110 struct fsl_esdhc_cfg usdhc_cfg[2] = {
111 {USDHC3_BASE_ADDR},
112 {USDHC4_BASE_ADDR},
113 };
114
board_mmc_get_env_dev(int devno)115 int board_mmc_get_env_dev(int devno)
116 {
117 return devno - 2;
118 }
119
board_mmc_getcd(struct mmc * mmc)120 int board_mmc_getcd(struct mmc *mmc)
121 {
122 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
123 int ret;
124
125 if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
126 gpio_direction_input(IMX_GPIO_NR(6, 11));
127 ret = !gpio_get_value(IMX_GPIO_NR(6, 11));
128 } else /* Don't have the CD GPIO pin on board */
129 ret = 1;
130
131 return ret;
132 }
133
board_mmc_init(struct bd_info * bis)134 int board_mmc_init(struct bd_info *bis)
135 {
136 int ret;
137 u32 index = 0;
138
139 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
140 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
141
142 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
143 switch (index) {
144 case 0:
145 imx_iomux_v3_setup_multiple_pads(
146 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
147 break;
148 case 1:
149 imx_iomux_v3_setup_multiple_pads(
150 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
151 break;
152 default:
153 printf("Warning: you configured more USDHC controllers"
154 "(%d) then supported by the board (%d)\n",
155 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
156 return -EINVAL;
157 }
158
159 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
160 if (ret)
161 return ret;
162 }
163
164 return 0;
165 }
166 #endif
167
168 #define MII_MMD_ACCESS_CTRL_REG 0xd
169 #define MII_MMD_ACCESS_ADDR_DATA_REG 0xe
170 #define MII_DBG_PORT_REG 0x1d
171 #define MII_DBG_PORT2_REG 0x1e
172
fecmxc_mii_postcall(int phy)173 int fecmxc_mii_postcall(int phy)
174 {
175 unsigned short val;
176
177 /*
178 * Due to the i.MX6Q Armadillo2 board HW design,there is
179 * no 125Mhz clock input from SOC. In order to use RGMII,
180 * We need enable AR8031 ouput a 125MHz clk from CLK_25M
181 */
182 miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7);
183 miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016);
184 miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007);
185 miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val);
186 val &= 0xffe3;
187 val |= 0x18;
188 miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val);
189
190 /* For the RGMII phy, we need enable tx clock delay */
191 miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5);
192 miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val);
193 val |= 0x0100;
194 miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val);
195
196 miiphy_write("FEC", phy, MII_BMCR, 0xa100);
197
198 return 0;
199 }
200
board_eth_init(struct bd_info * bis)201 int board_eth_init(struct bd_info *bis)
202 {
203 struct eth_device *dev;
204 int ret = cpu_eth_init(bis);
205
206 if (ret)
207 return ret;
208
209 dev = eth_get_dev_by_name("FEC");
210 if (!dev) {
211 printf("FEC MXC: Unable to get FEC device entry\n");
212 return -EINVAL;
213 }
214
215 ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
216 if (ret) {
217 printf("FEC MXC: Unable to register FEC mii postcall\n");
218 return ret;
219 }
220
221 return 0;
222 }
223
224 #ifdef CONFIG_USB_EHCI_MX6
225 #define USB_OTHERREGS_OFFSET 0x800
226 #define UCTRL_PWR_POL (1 << 9)
227
228 static iomux_v3_cfg_t const usb_otg_pads[] = {
229 MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
230 MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
231 };
232
setup_usb(void)233 static void setup_usb(void)
234 {
235 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
236 ARRAY_SIZE(usb_otg_pads));
237
238 /*
239 * set daisy chain for otg_pin_id on 6q.
240 * for 6dl, this bit is reserved
241 */
242 imx_iomux_set_gpr_register(1, 13, 1, 1);
243 }
244
board_ehci_hcd_init(int port)245 int board_ehci_hcd_init(int port)
246 {
247 u32 *usbnc_usb_ctrl;
248
249 if (port > 0)
250 return -EINVAL;
251
252 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
253 port * 4);
254
255 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
256
257 return 0;
258 }
259 #endif
260
board_early_init_f(void)261 int board_early_init_f(void)
262 {
263 setup_iomux_uart();
264 setup_iomux_enet();
265
266 return 0;
267 }
268
board_init(void)269 int board_init(void)
270 {
271 /* address of boot parameters */
272 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
273
274 #ifdef CONFIG_USB_EHCI_MX6
275 setup_usb();
276 #endif
277
278 return 0;
279 }
280
checkboard(void)281 int checkboard(void)
282 {
283 #ifdef CONFIG_MX6DL
284 puts("Board: MX6DL-Armadillo2\n");
285 #else
286 puts("Board: MX6Q-Armadillo2\n");
287 #endif
288
289 return 0;
290 }
291