1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 *
5 * Author: Ye Li <ye.li@nxp.com>
6 */
7
8 #include <init.h>
9 #include <net.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/global_data.h>
17 #include <asm/gpio.h>
18 #include <asm/mach-imx/iomux-v3.h>
19 #include <asm/mach-imx/boot_mode.h>
20 #include <asm/io.h>
21 #include <linux/delay.h>
22 #include <linux/sizes.h>
23 #include <common.h>
24 #include <fsl_esdhc_imx.h>
25 #include <miiphy.h>
26 #include <netdev.h>
27 #include <power/pmic.h>
28 #include <power/pfuze100_pmic.h>
29 #include "../common/pfuze.h"
30 #include <usb.h>
31 #include <usb/ehci-ci.h>
32 #include <pca953x.h>
33
34 DECLARE_GLOBAL_DATA_PTR;
35
36 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
37 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
38 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
39
40 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
41 PAD_CTL_SPEED_HIGH | \
42 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
43
44 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
45 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
46
47 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
48 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
49
50 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
51 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
52 PAD_CTL_SRE_FAST)
53 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
54
dram_init(void)55 int dram_init(void)
56 {
57 gd->ram_size = imx_ddr_size();
58
59 return 0;
60 }
61
62 static iomux_v3_cfg_t const uart1_pads[] = {
63 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
64 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
65 };
66
67 static iomux_v3_cfg_t const fec2_pads[] = {
68 MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
69 MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
70 MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
71 MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
72 MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
73 MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
74 MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
75 MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
76 MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
77 MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
78 MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
79 MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
80 MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
81 MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 };
83
setup_iomux_uart(void)84 static void setup_iomux_uart(void)
85 {
86 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
87 }
88
setup_fec(void)89 static int setup_fec(void)
90 {
91 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
92
93 /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */
94 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);
95
96 return enable_fec_anatop_clock(1, ENET_125MHZ);
97 }
98
board_eth_init(struct bd_info * bis)99 int board_eth_init(struct bd_info *bis)
100 {
101 int ret;
102
103 imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
104 setup_fec();
105
106 ret = fecmxc_initialize_multi(bis, 1,
107 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
108 if (ret)
109 printf("FEC%d MXC: %s:failed\n", 1, __func__);
110
111 return ret;
112 }
113
board_phy_config(struct phy_device * phydev)114 int board_phy_config(struct phy_device *phydev)
115 {
116 /*
117 * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
118 * Phy control debug reg 0
119 */
120 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
121 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
122
123 /* rgmii tx clock delay enable */
124 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
125 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
126
127 if (phydev->drv->config)
128 phydev->drv->config(phydev);
129
130 return 0;
131 }
132
power_init_board(void)133 int power_init_board(void)
134 {
135 struct udevice *dev;
136 int ret;
137 u32 dev_id, rev_id, i;
138 u32 switch_num = 6;
139 u32 offset = PFUZE100_SW1CMODE;
140
141 ret = pmic_get("pfuze100", &dev);
142 if (ret == -ENODEV)
143 return 0;
144
145 if (ret != 0)
146 return ret;
147
148 dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
149 rev_id = pmic_reg_read(dev, PFUZE100_REVID);
150 printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
151
152
153 /* Init mode to APS_PFM */
154 pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
155
156 for (i = 0; i < switch_num - 1; i++)
157 pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
158
159 /* set SW1AB staby volatage 0.975V */
160 pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
161
162 /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
163 pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
164
165 /* set SW1C staby volatage 1.10V */
166 pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20);
167
168 /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
169 pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
170
171 return 0;
172 }
173
174 #ifdef CONFIG_USB_EHCI_MX6
175 #define USB_OTHERREGS_OFFSET 0x800
176 #define UCTRL_PWR_POL (1 << 9)
177
178 static iomux_v3_cfg_t const usb_otg_pads[] = {
179 /* OGT1 */
180 MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
181 MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
182 /* OTG2 */
183 MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
184 };
185
setup_usb(void)186 static void setup_usb(void)
187 {
188 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
189 ARRAY_SIZE(usb_otg_pads));
190 }
191
board_usb_phy_mode(int port)192 int board_usb_phy_mode(int port)
193 {
194 if (port == 1)
195 return USB_INIT_HOST;
196 else
197 return usb_phy_mode(port);
198 }
199
board_ehci_hcd_init(int port)200 int board_ehci_hcd_init(int port)
201 {
202 u32 *usbnc_usb_ctrl;
203
204 if (port > 1)
205 return -EINVAL;
206
207 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
208 port * 4);
209
210 /* Set Power polarity */
211 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
212
213 return 0;
214 }
215 #endif
216
board_early_init_f(void)217 int board_early_init_f(void)
218 {
219 setup_iomux_uart();
220
221 return 0;
222 }
223
224 #ifdef CONFIG_FSL_QSPI
board_qspi_init(void)225 int board_qspi_init(void)
226 {
227 /* Set the clock */
228 enable_qspi_clk(0);
229
230 return 0;
231 }
232 #endif
233
234 #ifdef CONFIG_NAND_MXS
235 iomux_v3_cfg_t gpmi_pads[] = {
236 MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
237 MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
238 MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
239 MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
240 MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
241 MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
242 MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
243 MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
244 MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
245 MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
246 MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
247 MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
248 MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
249 MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
250 MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
251 };
252
setup_gpmi_nand(void)253 static void setup_gpmi_nand(void)
254 {
255 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
256
257 /* config gpmi nand iomux */
258 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
259
260 setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) |
261 MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) |
262 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3)));
263
264 /* enable apbh clock gating */
265 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
266 }
267 #endif
268
board_init(void)269 int board_init(void)
270 {
271 struct gpio_desc desc;
272 int ret;
273
274 /* Address of boot parameters */
275 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
276
277 ret = dm_gpio_lookup_name("gpio@30_4", &desc);
278 if (ret)
279 return ret;
280
281 ret = dm_gpio_request(&desc, "cpu_per_rst_b");
282 if (ret)
283 return ret;
284 /* Reset CPU_PER_RST_B signal for enet phy and PCIE */
285 dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
286 udelay(500);
287 dm_gpio_set_value(&desc, 1);
288
289 ret = dm_gpio_lookup_name("gpio@32_2", &desc);
290 if (ret)
291 return ret;
292
293 ret = dm_gpio_request(&desc, "steer_enet");
294 if (ret)
295 return ret;
296
297 dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
298 udelay(500);
299 /* Set steering signal to L for selecting B0 */
300 dm_gpio_set_value(&desc, 0);
301
302 #ifdef CONFIG_USB_EHCI_MX6
303 setup_usb();
304 #endif
305
306 #ifdef CONFIG_FSL_QSPI
307 board_qspi_init();
308 #endif
309
310 #ifdef CONFIG_NAND_MXS
311 setup_gpmi_nand();
312 #endif
313
314 return 0;
315 }
316
317 #ifdef CONFIG_CMD_BMODE
318 static const struct boot_mode board_boot_modes[] = {
319 {"sda", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)},
320 {"sdb", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
321 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
322 {"nand", MAKE_CFGVAL(0x82, 0x00, 0x00, 0x00)},
323 {NULL, 0},
324 };
325 #endif
326
board_late_init(void)327 int board_late_init(void)
328 {
329 #ifdef CONFIG_CMD_BMODE
330 add_board_boot_modes(board_boot_modes);
331 #endif
332
333 return 0;
334 }
335
checkboard(void)336 int checkboard(void)
337 {
338 puts("Board: MX6SX SABRE AUTO\n");
339
340 return 0;
341 }
342