1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2014 Freescale Semiconductor, Inc. 4 */ 5 6#define __ASSEMBLY__ 7#include <config.h> 8 9/* image version */ 10 11IMAGE_VERSION 2 12 13/* 14 * Boot Device : one of 15 * spi/sd/nand/onenand, qspi/nor 16 */ 17 18BOOT_FROM sd 19 20/* 21 * Secure boot support 22 */ 23#ifdef CONFIG_IMX_HAB 24CSF CONFIG_CSF_SIZE 25#endif 26 27/* 28 * Device Configuration Data (DCD) 29 * 30 * Each entry must have the format: 31 * Addr-type Address Value 32 * 33 * where: 34 * Addr-type register length (1,2 or 4 bytes) 35 * Address absolute address of the register 36 * value value to be stored in the register 37 */ 38 39/* Enable all clocks */ 40DATA 4 0x020c4068 0xffffffff 41DATA 4 0x020c406c 0xffffffff 42DATA 4 0x020c4070 0xffffffff 43DATA 4 0x020c4074 0xffffffff 44DATA 4 0x020c4078 0xffffffff 45DATA 4 0x020c407c 0xffffffff 46DATA 4 0x020c4080 0xffffffff 47DATA 4 0x020c4084 0xffffffff 48 49/* IOMUX - DDR IO Type */ 50DATA 4 0x020e0618 0x000c0000 51DATA 4 0x020e05fc 0x00000000 52 53/* Clock */ 54DATA 4 0x020e032c 0x00000030 55 56/* Address */ 57DATA 4 0x020e0300 0x00000020 58DATA 4 0x020e02fc 0x00000020 59DATA 4 0x020e05f4 0x00000020 60 61/* Control */ 62DATA 4 0x020e0340 0x00000020 63 64DATA 4 0x020e0320 0x00000000 65DATA 4 0x020e0310 0x00000020 66DATA 4 0x020e0314 0x00000020 67DATA 4 0x020e0614 0x00000020 68 69/* Data Strobe */ 70DATA 4 0x020e05f8 0x00020000 71DATA 4 0x020e0330 0x00000028 72DATA 4 0x020e0334 0x00000028 73DATA 4 0x020e0338 0x00000028 74DATA 4 0x020e033c 0x00000028 75 76/* Data */ 77DATA 4 0x020e0608 0x00020000 78DATA 4 0x020e060c 0x00000028 79DATA 4 0x020e0610 0x00000028 80DATA 4 0x020e061c 0x00000028 81DATA 4 0x020e0620 0x00000028 82DATA 4 0x020e02ec 0x00000028 83DATA 4 0x020e02f0 0x00000028 84DATA 4 0x020e02f4 0x00000028 85DATA 4 0x020e02f8 0x00000028 86 87/* Calibrations - ZQ */ 88DATA 4 0x021b0800 0xa1390003 89 90/* Write leveling */ 91DATA 4 0x021b080c 0x00290025 92DATA 4 0x021b0810 0x00220022 93 94/* DQS Read Gate */ 95DATA 4 0x021b083c 0x41480144 96DATA 4 0x021b0840 0x01340130 97 98/* Read/Write Delay */ 99DATA 4 0x021b0848 0x3C3E4244 100DATA 4 0x021b0850 0x34363638 101 102/* Read data bit delay */ 103DATA 4 0x021b081c 0x33333333 104DATA 4 0x021b0820 0x33333333 105DATA 4 0x021b0824 0x33333333 106DATA 4 0x021b0828 0x33333333 107 108/* Complete calibration by forced measurement */ 109DATA 4 0x021b08b8 0x00000800 110 111/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */ 112DATA 4 0x021b0004 0x0002002d 113DATA 4 0x021b0008 0x00333030 114DATA 4 0x021b000c 0x676b52f3 115DATA 4 0x021b0010 0xb66d8b63 116DATA 4 0x021b0014 0x01ff00db 117DATA 4 0x021b0018 0x00011740 118DATA 4 0x021b001c 0x00008000 119DATA 4 0x021b002c 0x000026d2 120DATA 4 0x021b0030 0x006b1023 121DATA 4 0x021b0040 0x0000005f 122DATA 4 0x021b0000 0x84190000 123 124/* Initialize MT41K256M16HA-125 - MR2 */ 125DATA 4 0x021b001c 0x04008032 126/* MR3 */ 127DATA 4 0x021b001c 0x00008033 128/* MR1 */ 129DATA 4 0x021b001c 0x00048031 130/* MR0 */ 131DATA 4 0x021b001c 0x05208030 132/* DDR device ZQ calibration */ 133DATA 4 0x021b001c 0x04008040 134 135/* Final DDR setup, before operation start */ 136DATA 4 0x021b0020 0x00000800 137DATA 4 0x021b0818 0x00011117 138DATA 4 0x021b001c 0x00000000 139