1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * Copyright 2020 NXP
5 */
6
7 #include <common.h>
8 #include <command.h>
9 #include <image.h>
10 #include <init.h>
11 #include <net.h>
12 #include <asm/global_data.h>
13 #include <asm/processor.h>
14 #include <asm/mmu.h>
15 #include <asm/cache.h>
16 #include <asm/immap_85xx.h>
17 #include <asm/io.h>
18 #include <env.h>
19 #include <miiphy.h>
20 #include <linux/libfdt.h>
21 #include <fdt_support.h>
22 #include <fsl_mdio.h>
23 #include <tsec.h>
24 #include <mmc.h>
25 #include <netdev.h>
26 #include <pci.h>
27 #include <asm/fsl_serdes.h>
28 #include <fsl_ifc.h>
29 #include <asm/fsl_pci.h>
30 #include <hwconfig.h>
31 #include <i2c.h>
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 #define GPIO4_PCIE_RESET_SET 0x08000000
36 #define MUX_CPLD_CAN_UART 0x00
37 #define MUX_CPLD_TDM 0x01
38 #define MUX_CPLD_SPICS0_FLASH 0x00
39 #define MUX_CPLD_SPICS0_SLIC 0x02
40 #define PMUXCR1_IFC_MASK 0x00ffff00
41 #define PMUXCR1_SDHC_MASK 0x00fff000
42 #define PMUXCR1_SDHC_ENABLE 0x00555000
43
44 enum {
45 MUX_TYPE_IFC,
46 MUX_TYPE_SDHC,
47 MUX_TYPE_SPIFLASH,
48 MUX_TYPE_TDM,
49 MUX_TYPE_CAN,
50 MUX_TYPE_CS0_NOR,
51 MUX_TYPE_CS0_NAND,
52 };
53
54 enum {
55 I2C_READ_BANK,
56 I2C_READ_PCB_VER,
57 };
58
59 static uint sd_ifc_mux;
60
61 struct cpld_data {
62 u8 cpld_ver; /* cpld revision */
63 #if defined(CONFIG_TARGET_P1010RDB_PA)
64 u8 pcba_ver; /* pcb revision number */
65 u8 twindie_ddr3;
66 u8 res1[6];
67 u8 bank_sel; /* NOR Flash bank */
68 u8 res2[5];
69 u8 usb2_sel;
70 u8 res3[1];
71 u8 porsw_sel;
72 u8 tdm_can_sel;
73 u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
74 u8 por0; /* POR Options */
75 u8 por1; /* POR Options */
76 u8 por2; /* POR Options */
77 u8 por3; /* POR Options */
78 #elif defined(CONFIG_TARGET_P1010RDB_PB)
79 u8 rom_loc;
80 #endif
81 };
82
board_early_init_f(void)83 int board_early_init_f(void)
84 {
85 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
86 struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
87 /* Clock configuration to access CPLD using IFC(GPCM) */
88 setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
89 /*
90 * Reset PCIe slots via GPIO4
91 */
92 setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
93 setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
94
95 return 0;
96 }
97
board_early_init_r(void)98 int board_early_init_r(void)
99 {
100 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
101 int flash_esel = find_tlb_idx((void *)flashbase, 1);
102
103 /*
104 * Remap Boot flash region to caching-inhibited
105 * so that flash can be erased properly.
106 */
107
108 /* Flush d-cache and invalidate i-cache of any FLASH data */
109 flush_dcache();
110 invalidate_icache();
111
112 if (flash_esel == -1) {
113 /* very unlikely unless something is messed up */
114 puts("Error: Could not find TLB for FLASH BASE\n");
115 flash_esel = 2; /* give our best effort to continue */
116 } else {
117 /* invalidate existing TLB entry for flash */
118 disable_tlb(flash_esel);
119 }
120
121 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
122 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
123 0, flash_esel, BOOKE_PAGESZ_16M, 1);
124
125 set_tlb(1, flashbase + 0x1000000,
126 CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
127 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
128 0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
129 return 0;
130 }
131
132 #if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
pci_init_board(void)133 void pci_init_board(void)
134 {
135 fsl_pcie_init_board(0);
136 }
137 #endif /* ifdef CONFIG_PCI */
138
config_board_mux(int ctrl_type)139 int config_board_mux(int ctrl_type)
140 {
141 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
142 u8 tmp;
143
144 #if CONFIG_IS_ENABLED(DM_I2C)
145 struct udevice *dev;
146 int ret;
147 #if defined(CONFIG_TARGET_P1010RDB_PA)
148 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
149
150 ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
151 I2C_PCA9557_ADDR1, 1, &dev);
152 if (ret) {
153 printf("%s: Cannot find udev for a bus %d\n",
154 __func__, I2C_PCA9557_BUS_NUM);
155 return ret;
156 }
157 switch (ctrl_type) {
158 case MUX_TYPE_IFC:
159 tmp = 0xf0;
160 dm_i2c_write(dev, 3, &tmp, 1);
161 tmp = 0x01;
162 dm_i2c_write(dev, 1, &tmp, 1);
163 sd_ifc_mux = MUX_TYPE_IFC;
164 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
165 break;
166 case MUX_TYPE_SDHC:
167 tmp = 0xf0;
168 dm_i2c_write(dev, 3, &tmp, 1);
169 tmp = 0x05;
170 dm_i2c_write(dev, 1, &tmp, 1);
171 sd_ifc_mux = MUX_TYPE_SDHC;
172 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
173 PMUXCR1_SDHC_ENABLE);
174 break;
175 case MUX_TYPE_SPIFLASH:
176 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
177 break;
178 case MUX_TYPE_TDM:
179 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
180 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
181 break;
182 case MUX_TYPE_CAN:
183 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
184 break;
185 default:
186 break;
187 }
188 #elif defined(CONFIG_TARGET_P1010RDB_PB)
189 ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
190 I2C_PCA9557_ADDR2, 1, &dev);
191 if (ret) {
192 printf("%s: Cannot find udev for a bus %d\n",
193 __func__, I2C_PCA9557_BUS_NUM);
194 return ret;
195 }
196 switch (ctrl_type) {
197 case MUX_TYPE_IFC:
198 dm_i2c_read(dev, 0, &tmp, 1);
199 clrbits_8(&tmp, 0x04);
200 dm_i2c_write(dev, 1, &tmp, 1);
201 dm_i2c_read(dev, 3, &tmp, 1);
202 clrbits_8(&tmp, 0x04);
203 dm_i2c_write(dev, 3, &tmp, 1);
204 sd_ifc_mux = MUX_TYPE_IFC;
205 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
206 break;
207 case MUX_TYPE_SDHC:
208 dm_i2c_read(dev, 0, &tmp, 1);
209 setbits_8(&tmp, 0x04);
210 dm_i2c_write(dev, 1, &tmp, 1);
211 dm_i2c_read(dev, 3, &tmp, 1);
212 clrbits_8(&tmp, 0x04);
213 dm_i2c_write(dev, 3, &tmp, 1);
214 sd_ifc_mux = MUX_TYPE_SDHC;
215 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
216 PMUXCR1_SDHC_ENABLE);
217 break;
218 case MUX_TYPE_SPIFLASH:
219 dm_i2c_read(dev, 0, &tmp, 1);
220 clrbits_8(&tmp, 0x80);
221 dm_i2c_write(dev, 1, &tmp, 1);
222 dm_i2c_read(dev, 3, &tmp, 1);
223 clrbits_8(&tmp, 0x80);
224 dm_i2c_write(dev, 3, &tmp, 1);
225 break;
226 case MUX_TYPE_TDM:
227 dm_i2c_read(dev, 0, &tmp, 1);
228 setbits_8(&tmp, 0x82);
229 dm_i2c_write(dev, 1, &tmp, 1);
230 dm_i2c_read(dev, 3, &tmp, 1);
231 clrbits_8(&tmp, 0x82);
232 dm_i2c_write(dev, 3, &tmp, 1);
233 break;
234 case MUX_TYPE_CAN:
235 dm_i2c_read(dev, 0, &tmp, 1);
236 clrbits_8(&tmp, 0x02);
237 dm_i2c_write(dev, 1, &tmp, 1);
238 dm_i2c_read(dev, 3, &tmp, 1);
239 clrbits_8(&tmp, 0x02);
240 dm_i2c_write(dev, 3, &tmp, 1);
241 break;
242 case MUX_TYPE_CS0_NOR:
243 dm_i2c_read(dev, 0, &tmp, 1);
244 clrbits_8(&tmp, 0x08);
245 dm_i2c_write(dev, 1, &tmp, 1);
246 dm_i2c_read(dev, 3, &tmp, 1);
247 clrbits_8(&tmp, 0x08);
248 dm_i2c_write(dev, 3, &tmp, 1);
249 break;
250 case MUX_TYPE_CS0_NAND:
251 dm_i2c_read(dev, 0, &tmp, 1);
252 setbits_8(&tmp, 0x08);
253 dm_i2c_write(dev, 1, &tmp, 1);
254 dm_i2c_read(dev, 3, &tmp, 1);
255 clrbits_8(&tmp, 0x08);
256 dm_i2c_write(dev, 3, &tmp, 1);
257 break;
258 default:
259 break;
260 }
261 #endif
262 #else
263 #if defined(CONFIG_TARGET_P1010RDB_PA)
264 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
265
266 switch (ctrl_type) {
267 case MUX_TYPE_IFC:
268 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
269 tmp = 0xf0;
270 i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
271 tmp = 0x01;
272 i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
273 sd_ifc_mux = MUX_TYPE_IFC;
274 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
275 break;
276 case MUX_TYPE_SDHC:
277 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
278 tmp = 0xf0;
279 i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
280 tmp = 0x05;
281 i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
282 sd_ifc_mux = MUX_TYPE_SDHC;
283 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
284 PMUXCR1_SDHC_ENABLE);
285 break;
286 case MUX_TYPE_SPIFLASH:
287 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
288 break;
289 case MUX_TYPE_TDM:
290 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
291 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
292 break;
293 case MUX_TYPE_CAN:
294 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
295 break;
296 default:
297 break;
298 }
299 #elif defined(CONFIG_TARGET_P1010RDB_PB)
300 uint orig_bus = i2c_get_bus_num();
301 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
302
303 switch (ctrl_type) {
304 case MUX_TYPE_IFC:
305 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
306 clrbits_8(&tmp, 0x04);
307 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
308 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
309 clrbits_8(&tmp, 0x04);
310 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
311 sd_ifc_mux = MUX_TYPE_IFC;
312 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
313 break;
314 case MUX_TYPE_SDHC:
315 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
316 setbits_8(&tmp, 0x04);
317 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
318 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
319 clrbits_8(&tmp, 0x04);
320 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
321 sd_ifc_mux = MUX_TYPE_SDHC;
322 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
323 PMUXCR1_SDHC_ENABLE);
324 break;
325 case MUX_TYPE_SPIFLASH:
326 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
327 clrbits_8(&tmp, 0x80);
328 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
329 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
330 clrbits_8(&tmp, 0x80);
331 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
332 break;
333 case MUX_TYPE_TDM:
334 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
335 setbits_8(&tmp, 0x82);
336 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
337 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
338 clrbits_8(&tmp, 0x82);
339 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
340 break;
341 case MUX_TYPE_CAN:
342 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
343 clrbits_8(&tmp, 0x02);
344 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
345 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
346 clrbits_8(&tmp, 0x02);
347 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
348 break;
349 case MUX_TYPE_CS0_NOR:
350 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
351 clrbits_8(&tmp, 0x08);
352 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
353 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
354 clrbits_8(&tmp, 0x08);
355 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
356 break;
357 case MUX_TYPE_CS0_NAND:
358 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
359 setbits_8(&tmp, 0x08);
360 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
361 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
362 clrbits_8(&tmp, 0x08);
363 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
364 break;
365 default:
366 break;
367 }
368 i2c_set_bus_num(orig_bus);
369 #endif
370 #endif
371 return 0;
372 }
373
374 #ifdef CONFIG_TARGET_P1010RDB_PB
i2c_pca9557_read(int type)375 int i2c_pca9557_read(int type)
376 {
377 u8 val;
378 int bus_num = I2C_PCA9557_BUS_NUM;
379
380 #if CONFIG_IS_ENABLED(DM_I2C)
381 struct udevice *dev;
382 int ret;
383
384 ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA9557_ADDR2, 1, &dev);
385 if (ret) {
386 printf("%s: Cannot find udev for a bus %d\n",
387 __func__, bus_num);
388 return ret;
389 }
390 dm_i2c_read(dev, 0, &val, 1);
391 #else
392 i2c_set_bus_num(bus_num);
393 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
394 #endif
395
396 switch (type) {
397 case I2C_READ_BANK:
398 val = (val & 0x10) >> 4;
399 break;
400 case I2C_READ_PCB_VER:
401 val = ((val & 0x60) >> 5) + 1;
402 break;
403 default:
404 break;
405 }
406
407 return val;
408 }
409 #endif
410
checkboard(void)411 int checkboard(void)
412 {
413 struct cpu_type *cpu;
414 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
415 u8 val;
416
417 cpu = gd->arch.cpu;
418 #if defined(CONFIG_TARGET_P1010RDB_PA)
419 printf("Board: %sRDB-PA, ", cpu->name);
420 #elif defined(CONFIG_TARGET_P1010RDB_PB)
421 printf("Board: %sRDB-PB, ", cpu->name);
422 #if CONFIG_IS_ENABLED(DM_I2C)
423 struct udevice *dev;
424 int ret;
425
426 ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR2,
427 1, &dev);
428 if (ret) {
429 printf("%s: Cannot find udev for a bus %d\n", __func__,
430 I2C_PCA9557_BUS_NUM);
431 return ret;
432 }
433 val = 0x0; /* no polarity inversion */
434 dm_i2c_write(dev, 2, &val, 1);
435 #else
436 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
437 i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
438 val = 0x0; /* no polarity inversion */
439 i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
440 #endif
441 #endif
442
443 #ifdef CONFIG_SDCARD
444 /* switch to IFC to read info from CPLD */
445 config_board_mux(MUX_TYPE_IFC);
446 #endif
447
448 #if defined(CONFIG_TARGET_P1010RDB_PA)
449 val = (in_8(&cpld_data->pcba_ver) & 0xf);
450 printf("PCB: v%x.0\n", val);
451 #elif defined(CONFIG_TARGET_P1010RDB_PB)
452 val = in_8(&cpld_data->cpld_ver);
453 printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
454 printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
455 val = in_8(&cpld_data->rom_loc) & 0xf;
456 puts("Boot from: ");
457 switch (val) {
458 case 0xf:
459 config_board_mux(MUX_TYPE_CS0_NOR);
460 printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
461 break;
462 case 0xe:
463 puts("SDHC\n");
464 val = 0x60; /* set pca9557 pin input/output */
465 #if CONFIG_IS_ENABLED(DM_I2C)
466 dm_i2c_write(dev, 3, &val, 1);
467 #else
468 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
469 #endif
470 break;
471 case 0x5:
472 config_board_mux(MUX_TYPE_IFC);
473 config_board_mux(MUX_TYPE_CS0_NAND);
474 puts("NAND\n");
475 break;
476 case 0x6:
477 config_board_mux(MUX_TYPE_IFC);
478 puts("SPI\n");
479 break;
480 default:
481 puts("unknown\n");
482 break;
483 }
484 #endif
485 return 0;
486 }
487
488 #ifndef CONFIG_DM_ETH
board_eth_init(struct bd_info * bis)489 int board_eth_init(struct bd_info *bis)
490 {
491 #ifdef CONFIG_TSEC_ENET
492 struct fsl_pq_mdio_info mdio_info;
493 struct tsec_info_struct tsec_info[4];
494 struct cpu_type *cpu;
495 int num = 0;
496
497 cpu = gd->arch.cpu;
498
499 #ifdef CONFIG_TSEC1
500 SET_STD_TSEC_INFO(tsec_info[num], 1);
501 num++;
502 #endif
503 #ifdef CONFIG_TSEC2
504 SET_STD_TSEC_INFO(tsec_info[num], 2);
505 num++;
506 #endif
507 #ifdef CONFIG_TSEC3
508 /* P1014 and it's derivatives do not support eTSEC3 */
509 if (cpu->soc_ver != SVR_P1014) {
510 SET_STD_TSEC_INFO(tsec_info[num], 3);
511 num++;
512 }
513 #endif
514 if (!num) {
515 printf("No TSECs initialized\n");
516 return 0;
517 }
518
519 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
520 mdio_info.name = DEFAULT_MII_NAME;
521
522 fsl_pq_mdio_init(bis, &mdio_info);
523
524 tsec_eth_init(bis, tsec_info, num);
525 #endif
526
527 return pci_eth_init(bis);
528 }
529 #endif
530
531 #if defined(CONFIG_OF_BOARD_SETUP)
fdt_del_flexcan(void * blob)532 void fdt_del_flexcan(void *blob)
533 {
534 int nodeoff = 0;
535
536 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
537 "fsl,p1010-flexcan")) >= 0) {
538 fdt_del_node(blob, nodeoff);
539 }
540 }
541
fdt_del_spi_flash(void * blob)542 void fdt_del_spi_flash(void *blob)
543 {
544 int nodeoff = 0;
545
546 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
547 "spansion,s25sl12801")) >= 0) {
548 fdt_del_node(blob, nodeoff);
549 }
550 }
551
fdt_del_spi_slic(void * blob)552 void fdt_del_spi_slic(void *blob)
553 {
554 int nodeoff = 0;
555
556 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
557 "zarlink,le88266")) >= 0) {
558 fdt_del_node(blob, nodeoff);
559 }
560 }
561
fdt_del_tdm(void * blob)562 void fdt_del_tdm(void *blob)
563 {
564 int nodeoff = 0;
565
566 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
567 "fsl,starlite-tdm")) >= 0) {
568 fdt_del_node(blob, nodeoff);
569 }
570 }
571
fdt_del_sdhc(void * blob)572 void fdt_del_sdhc(void *blob)
573 {
574 int nodeoff = 0;
575
576 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
577 "fsl,esdhc")) >= 0) {
578 fdt_del_node(blob, nodeoff);
579 }
580 }
581
fdt_del_ifc(void * blob)582 void fdt_del_ifc(void *blob)
583 {
584 int nodeoff = 0;
585
586 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
587 "fsl,ifc")) >= 0) {
588 fdt_del_node(blob, nodeoff);
589 }
590 }
591
fdt_disable_uart1(void * blob)592 void fdt_disable_uart1(void *blob)
593 {
594 int nodeoff;
595
596 nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
597 CONFIG_SYS_NS16550_COM2);
598
599 if (nodeoff > 0) {
600 fdt_status_disabled(blob, nodeoff);
601 } else {
602 printf("WARNING unable to set status for fsl,ns16550 "
603 "uart1: %s\n", fdt_strerror(nodeoff));
604 }
605 }
606
ft_board_setup(void * blob,struct bd_info * bd)607 int ft_board_setup(void *blob, struct bd_info *bd)
608 {
609 phys_addr_t base;
610 phys_size_t size;
611 struct cpu_type *cpu;
612
613 cpu = gd->arch.cpu;
614
615 ft_cpu_setup(blob, bd);
616
617 base = env_get_bootm_low();
618 size = env_get_bootm_size();
619
620 #if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
621 FT_FSL_PCI_SETUP;
622 #endif
623
624 fdt_fixup_memory(blob, (u64)base, (u64)size);
625
626 #if defined(CONFIG_HAS_FSL_DR_USB)
627 fsl_fdt_fixup_dr_usb(blob, bd);
628 #endif
629
630 /* P1014 and it's derivatives don't support CAN and eTSEC3 */
631 if (cpu->soc_ver == SVR_P1014) {
632 fdt_del_flexcan(blob);
633 fdt_del_node_and_alias(blob, "ethernet2");
634 }
635
636 /* Delete IFC node as IFC pins are multiplexing with SDHC */
637 if (sd_ifc_mux != MUX_TYPE_IFC)
638 fdt_del_ifc(blob);
639 else
640 fdt_del_sdhc(blob);
641
642 if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
643 fdt_del_tdm(blob);
644 fdt_del_spi_slic(blob);
645 } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
646 fdt_del_flexcan(blob);
647 fdt_del_spi_flash(blob);
648 fdt_disable_uart1(blob);
649 } else {
650 /*
651 * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
652 * explicitly, defaultly spi_cs_sel to spi-flash instead of
653 * to tdm/slic.
654 */
655 fdt_del_tdm(blob);
656 fdt_del_flexcan(blob);
657 fdt_disable_uart1(blob);
658 }
659
660 return 0;
661 }
662 #endif
663
664 #ifdef CONFIG_SDCARD
board_mmc_init(struct bd_info * bis)665 int board_mmc_init(struct bd_info *bis)
666 {
667 config_board_mux(MUX_TYPE_SDHC);
668 return -1;
669 }
670 #else
board_reset(void)671 void board_reset(void)
672 {
673 /* mux to IFC to enable CPLD for reset */
674 if (sd_ifc_mux != MUX_TYPE_IFC)
675 config_board_mux(MUX_TYPE_IFC);
676 }
677 #endif
678
679
misc_init_r(void)680 int misc_init_r(void)
681 {
682 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
683
684 if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
685 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
686 MPC85xx_PMUXCR_CAN1_UART |
687 MPC85xx_PMUXCR_CAN2_TDM |
688 MPC85xx_PMUXCR_CAN2_UART);
689 config_board_mux(MUX_TYPE_CAN);
690 } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
691 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
692 MPC85xx_PMUXCR_CAN1_UART);
693 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
694 MPC85xx_PMUXCR_CAN1_TDM);
695 clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
696 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
697 config_board_mux(MUX_TYPE_TDM);
698 } else {
699 /* defaultly spi_cs_sel to flash */
700 config_board_mux(MUX_TYPE_SPIFLASH);
701 }
702
703 if (hwconfig("esdhc"))
704 config_board_mux(MUX_TYPE_SDHC);
705 else if (hwconfig("ifc"))
706 config_board_mux(MUX_TYPE_IFC);
707
708 #ifdef CONFIG_TARGET_P1010RDB_PB
709 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
710 #endif
711 return 0;
712 }
713
714 #ifndef CONFIG_SPL_BUILD
pin_mux_cmd(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])715 static int pin_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
716 char *const argv[])
717 {
718 if (argc < 2)
719 return CMD_RET_USAGE;
720 if (strcmp(argv[1], "ifc") == 0)
721 config_board_mux(MUX_TYPE_IFC);
722 else if (strcmp(argv[1], "sdhc") == 0)
723 config_board_mux(MUX_TYPE_SDHC);
724 else
725 return CMD_RET_USAGE;
726 return 0;
727 }
728
729 U_BOOT_CMD(
730 mux, 2, 0, pin_mux_cmd,
731 "configure multiplexing pin for IFC/SDHC bus in runtime",
732 "bus_type (e.g. mux sdhc)"
733 );
734 #endif
735