1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright 2013 Freescale Semiconductor, Inc.
3 */
4
5 #include <common.h>
6 #include <clock_legacy.h>
7 #include <console.h>
8 #include <env.h>
9 #include <env_internal.h>
10 #include <init.h>
11 #include <ns16550.h>
12 #include <malloc.h>
13 #include <mmc.h>
14 #include <nand.h>
15 #include <i2c.h>
16 #include <fsl_esdhc.h>
17 #include <spi_flash.h>
18 #include <asm/global_data.h>
19 #include "../common/spl.h"
20
21 DECLARE_GLOBAL_DATA_PTR;
22
get_effective_memsize(void)23 phys_size_t get_effective_memsize(void)
24 {
25 return CONFIG_SYS_L2_SIZE;
26 }
27
board_init_f(ulong bootflag)28 void board_init_f(ulong bootflag)
29 {
30 u32 plat_ratio;
31 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
32 struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
33
34 console_init_f();
35
36 /* Clock configuration to access CPLD using IFC(GPCM) */
37 setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
38
39 #ifdef CONFIG_TARGET_P1010RDB_PB
40 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
41 #endif
42
43 /* initialize selected port with appropriate baud rate */
44 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
45 plat_ratio >>= 1;
46 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
47
48 ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
49 gd->bus_clk / 16 / CONFIG_BAUDRATE);
50
51 #ifdef CONFIG_SPL_MMC_BOOT
52 puts("\nSD boot...\n");
53 #elif defined(CONFIG_SPL_SPI_BOOT)
54 puts("\nSPI Flash boot...\n");
55 #endif
56 /* copy code to RAM and jump to it - this should not return */
57 /* NOTE - code has to be copied out of NAND buffer before
58 * other blocks can be read.
59 */
60 relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
61 }
62
board_init_r(gd_t * gd,ulong dest_addr)63 void board_init_r(gd_t *gd, ulong dest_addr)
64 {
65 /* Pointer is writable since we allocated a register for it */
66 gd = (gd_t *)CONFIG_SPL_GD_ADDR;
67 struct bd_info *bd;
68
69 memset(gd, 0, sizeof(gd_t));
70 bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
71 memset(bd, 0, sizeof(struct bd_info));
72 gd->bd = bd;
73
74 arch_cpu_init();
75 get_clocks();
76 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
77 CONFIG_SPL_RELOC_MALLOC_SIZE);
78 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
79
80 #ifndef CONFIG_SPL_NAND_BOOT
81 env_init();
82 #endif
83 #ifdef CONFIG_SPL_MMC_BOOT
84 mmc_initialize(bd);
85 #endif
86
87 /* relocate environment function pointers etc. */
88 #ifdef CONFIG_SPL_NAND_BOOT
89 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
90 (uchar *)SPL_ENV_ADDR);
91 gd->env_addr = (ulong)(SPL_ENV_ADDR);
92 gd->env_valid = ENV_VALID;
93 #else
94 env_relocate();
95 #endif
96
97 i2c_init_all();
98
99 dram_init();
100 #ifdef CONFIG_SPL_NAND_BOOT
101 puts("\nTertiary program loader running in sram...");
102 #else
103 puts("\nSecond program loader running in sram...");
104 #endif
105
106 #ifdef CONFIG_SPL_MMC_BOOT
107 mmc_boot();
108 #elif defined(CONFIG_SPL_SPI_BOOT)
109 fsl_spi_boot();
110 #elif defined(CONFIG_SPL_NAND_BOOT)
111 nand_boot();
112 #endif
113 }
114