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| .. | 18-Mar-2022 | - | ||||
| Kconfig | A D | 18-Mar-2022 | 206 | 15 | 10 | |
| MAINTAINERS | A D | 18-Mar-2022 | 919 | 26 | 25 | |
| Makefile | A D | 18-Mar-2022 | 339 | 25 | 17 | |
| README | A D | 18-Mar-2022 | 2.5 KiB | 65 | 53 | |
| ddr.c | A D | 18-Mar-2022 | 7.1 KiB | 290 | 247 | |
| law.c | A D | 18-Mar-2022 | 662 | 23 | 15 | |
| p1_p2_rdb_pc.c | A D | 18-Mar-2022 | 10.3 KiB | 426 | 337 | |
| spl.c | A D | 18-Mar-2022 | 2.9 KiB | 123 | 91 | |
| spl_minimal.c | A D | 18-Mar-2022 | 1.5 KiB | 64 | 42 | |
| tlb.c | A D | 18-Mar-2022 | 3.5 KiB | 111 | 79 |
README
1Overview 2-------- 3P1_P2_RDB_PC represents a set of boards including 4 P1020MSBG-PC 5 P1020RDB-PC 6 P1020RDB-PD 7 P1021RDB-PC 8 P1024RDB 9 P2020RDB-PC 10 11They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC 12has 64-bit DDR. All others have 32-bit DDR. 13 14Key features on these boards include: 15 * DDR3 16 * NOR flash 17 * NAND flash (on RDB's only) 18 * SPI flash (on RDB's only) 19 * SDHC/MMC card slot 20 * VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB) 21 * PCIE slot and mini-PCIE slots 22 23As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM 24is used to store SPD data. In case of absent or corrupted SPD, falling back 25to timing data embedded in the source code will be used. Raw timing data is 26extracted from DDR chip datasheet. Different speeds of DDR are supported with 27this approach. ODT option is forced to fit this set of boards, again because 28they don't have regular DIMMs. 29 30CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet specification 31for writing timing. 32 33VSC firmware Address is defined by default in config file for eTSEC1. 34 35SD width is based off DIP switch. DIP switch is detected on the 36board by reading i2c bus and setting the appropriate mux values. 37 38Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC have 39pins multiplexing. QE function needs to be disabled to access Nor Flash and 40CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe" 41in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to 42enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below 43 44'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD. 45'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD. 46 47Device tree support and how to enable it for different configs 48-------------------------------------------------------------- 49Device tree support is available for p1020rdb and p2020rdb for below mentioned boot, 501. NOR Boot 512. NAND Boot 523. SD Boot 534. SPIFLASH Boot 54 55To enable device tree support for other boot, below configs need to be 56enabled in relative defconfig file, 571. CONFIG_DEFAULT_DEVICE_TREE="p1020rdb" (Change default device tree name if required) 582. CONFIG_OF_CONTROL 593. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at 60 CONFIG_RESET_VECTOR_ADDRESS - 0xffc 61 62If device tree support is enabled in defconfig, 631. use 'u-boot-with-dtb.bin' for NOR boot. 642. use 'u-boot-with-spl.bin' for other boot. 65