README
1Overview
2=========
3The P2041 Processor combines four Power Architecture processor cores
4with high-performance datapath acceleration architecture(DPAA), CoreNet
5fabric infrastructure, as well as network and peripheral bus interfaces
6required for networking, telecom/datacom, wireless infrastructure, and
7military/aerospace applications.
8
9P2041RDB board is a quad core platform supporting the P2041 processor
10of QorIQ DPAA series.
11
12Boot from NOR flash
13===================
141. Build image
15 make P2041RDB_config
16 make all
17
182. Program image
19 => tftp 1000000 u-boot.bin
20 => protect off all
21 => erase eff40000 efffffff
22 => cp.b 1000000 eff40000 c0000
23
243. Program RCW
25 => tftp 1000000 rcw.bin
26 => protect off all
27 => erase e8000000 e801ffff
28 => cp.b 1000000 e8000000 50
29
304. Program FMAN Firmware ucode
31 => tftp 1000000 ucode.bin
32 => protect off all
33 => erase eff00000 eff3ffff
34 => cp.b 1000000 eff00000 2000
35
365. Change DIP-switch
37 SW1[1-5] = 10110
38 Note: 1 stands for 'on', 0 stands for 'off'
39
40Boot from SDCard
41===================
421. Build image
43 make P2041RDB_SDCARD_config
44 make all
45
462. Generate PBL imge
47 Use PE tool to produce a image used to be programed to
48 SDCard which contains RCW and U-Boot image.
49
503. Program the PBL image to SDCard
51 => tftp 1000000 pbl_sd.bin
52 => mmcinfo
53 => mmc write 1000000 8 672
54
554. Program FMAN Firmware ucode
56 => tftp 1000000 ucode.bin
57 => mmc write 1000000 690 10
58
595. Change DIP-switch
60 SW1[1-5] = 01100
61 Note: 1 stands for 'on', 0 stands for 'off'
62
63Boot from SPI flash
64===================
651. Build image
66 make P2041RDB_SPIFLASH_config
67 make all
68
692. Generate PBL imge
70 Use PE tool to produce a image used to be programed to
71 SPI flash which contains RCW and U-Boot image.
72
733. Program the PBL image to SPI flash
74 => tftp 1000000 pbl_spi.bin
75 => spi probe 0
76 => sf erase 0 100000
77 => sf write 1000000 0 $filesize
78
794. Program FMAN Firmware ucode
80 => tftp 1000000 ucode.bin
81 => sf erase 110000 10000
82 => sf write 1000000 110000 $filesize
83
845. Change DIP-switch
85 SW1[1-5] = 10100
86 Note: 1 stands for 'on', 0 stands for 'off'
87
88Device tree support and how to enable it for different configs
89--------------------------------------------------------------
90Device tree support is available for p2041rdb for below mentioned boot,
911. NOR Boot
922. NAND Boot
933. SD Boot
944. SPIFLASH Boot
95
96To enable device tree support for other boot, below configs need to be
97enabled in relative defconfig file,
981. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required)
992. CONFIG_OF_CONTROL
1003. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
101 CONFIG_RESET_VECTOR_ADDRESS - 0xffc
102
103If device tree support is enabled in defconfig, use 'u-boot-with-dtb.bin'
104instead of u-boot.bin for all boot.
105
106CPLD command
107============
108The CPLD is used to control the power sequence and some serdes lane
109mux function.
110
111cpld reset - hard reset to default bank
112cpld reset altbank - reset to alternate bank
113cpld lane_mux <lane> <mux_value> - set multiplexed lane pin
114 lane 6: 0 -> slot1 (Default)
115 1 -> SGMII
116 lane a: 0 -> slot2 (Default)
117 1 -> AURORA
118 lane c: 0 -> slot2 (Default)
119 1 -> SATA0
120 lane d: 0 -> slot2 (Default)
121 1 -> SATA1
122
123Using the Device Tree Source File
124=================================
125To create the DTB (Device Tree Binary) image file, use a command
126similar to this:
127 dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb
128
129Or use the following command:
130 {linux-2.6}/make p2041rdb.dtb ARCH=powerpc
131
132then the dtb file will be generated under the following directory:
133 {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb
134
135Booting Linux
136=============
137Place a linux uImage in the TFTP disk area.
138 tftp 1000000 uImage
139 tftp 2000000 rootfs.ext2.gz.uboot
140 tftp 3000000 p2041rdb.dtb
141 bootm 1000000 2000000 3000000
142