1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Author: Mingkai Hu <Mingkai.hu@freescale.com>
5 */
6
7 /*
8 * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs
9 * are provided by the three on-board PHY or by the standard Freescale
10 * four-port SGMII riser card. We need to change the phy-handle in the
11 * kernel dts file to point to the correct PHY according to serdes mux
12 * and serdes protocol selection.
13 */
14
15 #include <common.h>
16 #include <net.h>
17 #include <netdev.h>
18 #include <asm/fsl_serdes.h>
19 #include <fm_eth.h>
20 #include <fsl_mdio.h>
21 #include <malloc.h>
22 #include <fsl_dtsec.h>
23
24 #include "cpld.h"
25 #include "../common/fman.h"
26
27 #ifdef CONFIG_FMAN_ENET
28 /*
29 * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
30 * that the mapping must be determined dynamically, or that the lane maps to
31 * something other than a board slot
32 */
33 static u8 lane_to_slot[] = {
34 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0
35 };
36
37 static int riser_phy_addr[] = {
38 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
39 CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
40 CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
41 CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
42 };
43
44 /*
45 * Initialize the lane_to_slot[] array.
46 *
47 * On the P2040RDB board the mapping is controlled by CPLD register.
48 */
initialize_lane_to_slot(void)49 static void initialize_lane_to_slot(void)
50 {
51 u8 mux = CPLD_READ(serdes_mux);
52
53 lane_to_slot[6] = (mux & SERDES_MUX_LANE_6_MASK) ? 0 : 1;
54 lane_to_slot[10] = (mux & SERDES_MUX_LANE_A_MASK) ? 0 : 2;
55 lane_to_slot[12] = (mux & SERDES_MUX_LANE_C_MASK) ? 0 : 2;
56 lane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2;
57 }
58
59 /*
60 * Given the following ...
61 *
62 * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
63 * compatible string and 'addr' physical address)
64 *
65 * 2) An Fman port
66 *
67 * ... update the phy-handle property of the Ethernet node to point to the
68 * right PHY. This assumes that we already know the PHY for each port.
69 *
70 * The offset of the Fman Ethernet node is also passed in for convenience, but
71 * it is not used, and we recalculate the offset anyway.
72 *
73 * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
74 * Inside the Fman, "ports" are things that connect to MACs. We only call them
75 * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
76 * and ports are the same thing.
77 *
78 */
board_ft_fman_fixup_port(void * fdt,char * compat,phys_addr_t addr,enum fm_port port,int offset)79 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
80 enum fm_port port, int offset)
81 {
82 phy_interface_t intf = fm_info_get_enet_if(port);
83 char phy[16];
84 int lane;
85 u8 slot;
86
87 switch (intf) {
88 /* The RGMII PHY is identified by the MAC connected to it */
89 case PHY_INTERFACE_MODE_RGMII:
90 case PHY_INTERFACE_MODE_RGMII_TXID:
91 case PHY_INTERFACE_MODE_RGMII_RXID:
92 case PHY_INTERFACE_MODE_RGMII_ID:
93 sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1);
94 fdt_set_phy_handle(fdt, compat, addr, phy);
95 break;
96 /* The SGMII PHY is identified by the MAC connected to it */
97 case PHY_INTERFACE_MODE_SGMII:
98 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port);
99 if (lane < 0)
100 return;
101 slot = lane_to_slot[lane];
102 if (slot) {
103 sprintf(phy, "phy_sgmii_%x",
104 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
105 + (port - FM1_DTSEC1));
106 fdt_set_phy_handle(fdt, compat, addr, phy);
107 } else {
108 sprintf(phy, "phy_sgmii_%x",
109 CONFIG_SYS_FM1_DTSEC1_PHY_ADDR
110 + (port - FM1_DTSEC1));
111 fdt_set_phy_handle(fdt, compat, addr, phy);
112 }
113 break;
114 case PHY_INTERFACE_MODE_XGMII:
115 /* XAUI */
116 lane = serdes_get_first_lane(XAUI_FM1);
117 if (lane >= 0) {
118 /* The XAUI PHY is identified by the slot */
119 sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
120 fdt_set_phy_handle(fdt, compat, addr, phy);
121 }
122 break;
123 default:
124 break;
125 }
126 }
127 #endif /* #ifdef CONFIG_FMAN_ENET */
128
board_eth_init(struct bd_info * bis)129 int board_eth_init(struct bd_info *bis)
130 {
131 #ifdef CONFIG_FMAN_ENET
132 struct fsl_pq_mdio_info dtsec_mdio_info;
133 struct tgec_mdio_info tgec_mdio_info;
134 unsigned int i, slot;
135 int lane;
136
137 printf("Initializing Fman\n");
138
139 initialize_lane_to_slot();
140
141 dtsec_mdio_info.regs =
142 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
143 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
144
145 /* Register the real 1G MDIO bus */
146 fsl_pq_mdio_init(bis, &dtsec_mdio_info);
147
148 tgec_mdio_info.regs =
149 (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
150 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
151
152 /* Register the real 10G MDIO bus */
153 fm_tgec_mdio_init(bis, &tgec_mdio_info);
154
155 /*
156 * Program the three on-board SGMII PHY addresses. If the SGMII Riser
157 * card used, we'll override the PHY address later. For any DTSEC that
158 * is RGMII, we'll also override its PHY address later. We assume that
159 * DTSEC4 and DTSEC5 are used for RGMII.
160 */
161 fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
162 fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
163 fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
164
165 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
166 int idx = i - FM1_DTSEC1;
167
168 switch (fm_info_get_enet_if(i)) {
169 case PHY_INTERFACE_MODE_SGMII:
170 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
171 if (lane < 0)
172 break;
173 slot = lane_to_slot[lane];
174 if (slot)
175 fm_info_set_phy_address(i, riser_phy_addr[i]);
176 break;
177 case PHY_INTERFACE_MODE_RGMII:
178 case PHY_INTERFACE_MODE_RGMII_TXID:
179 case PHY_INTERFACE_MODE_RGMII_RXID:
180 case PHY_INTERFACE_MODE_RGMII_ID:
181 /* Only DTSEC4 and DTSEC5 can be routed to RGMII */
182 fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
183 CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
184 CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
185 break;
186 default:
187 printf("Fman1: DTSEC%u set to unknown interface %i\n",
188 idx + 1, fm_info_get_enet_if(i));
189 break;
190 }
191
192 fm_info_set_mdio(i,
193 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
194 }
195
196 lane = serdes_get_first_lane(XAUI_FM1);
197 if (lane >= 0) {
198 slot = lane_to_slot[lane];
199 if (slot)
200 fm_info_set_phy_address(FM1_10GEC1,
201 CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
202 }
203
204 fm_info_set_mdio(FM1_10GEC1,
205 miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
206 cpu_eth_init(bis);
207 #endif
208
209 return pci_eth_init(bis);
210 }
211