1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2013-2015, Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <init.h>
8 #include <asm/global_data.h>
9 #include <asm/io.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/siul.h>
12 #include <asm/arch/lpddr2.h>
13 #include <asm/arch/clock.h>
14 #include <mmc.h>
15 #include <fsl_esdhc_imx.h>
16 #include <miiphy.h>
17 #include <netdev.h>
18 #include <i2c.h>
19
20 DECLARE_GLOBAL_DATA_PTR;
21
setup_iomux_ddr(void)22 void setup_iomux_ddr(void)
23 {
24 lpddr2_config_iomux(DDR0);
25 lpddr2_config_iomux(DDR1);
26
27 }
28
ddr_phy_init(void)29 void ddr_phy_init(void)
30 {
31 }
32
ddr_ctrl_init(void)33 void ddr_ctrl_init(void)
34 {
35 config_mmdc(0);
36 config_mmdc(1);
37 }
38
dram_init(void)39 int dram_init(void)
40 {
41 setup_iomux_ddr();
42
43 ddr_ctrl_init();
44
45 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
46
47 return 0;
48 }
49
setup_iomux_uart(void)50 static void setup_iomux_uart(void)
51 {
52 /* Muxing for linflex */
53 /* Replace the magic values after bringup */
54
55 /* set TXD - MSCR[12] PA12 */
56 writel(SIUL2_UART_TXD, SIUL2_MSCRn(SIUL2_UART0_TXD_PAD));
57
58 /* set RXD - MSCR[11] - PA11 */
59 writel(SIUL2_UART_MSCR_RXD, SIUL2_MSCRn(SIUL2_UART0_MSCR_RXD_PAD));
60
61 /* set RXD - IMCR[200] - 200 */
62 writel(SIUL2_UART_IMCR_RXD, SIUL2_IMCRn(SIUL2_UART0_IMCR_RXD_PAD));
63 }
64
setup_iomux_enet(void)65 static void setup_iomux_enet(void)
66 {
67 }
68
setup_iomux_i2c(void)69 static void setup_iomux_i2c(void)
70 {
71 }
72
73 #ifdef CONFIG_SYS_USE_NAND
setup_iomux_nfc(void)74 void setup_iomux_nfc(void)
75 {
76 }
77 #endif
78
79 #ifdef CONFIG_FSL_ESDHC_IMX
80 struct fsl_esdhc_cfg esdhc_cfg[1] = {
81 {USDHC_BASE_ADDR},
82 };
83
board_mmc_getcd(struct mmc * mmc)84 int board_mmc_getcd(struct mmc *mmc)
85 {
86 /* eSDHC1 is always present */
87 return 1;
88 }
89
board_mmc_init(struct bd_info * bis)90 int board_mmc_init(struct bd_info * bis)
91 {
92 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);
93
94 /* Set iomux PADS for USDHC */
95
96 /* PK6 pad: uSDHC clk */
97 writel(SIUL2_USDHC_PAD_CTRL_CLK, SIUL2_MSCRn(150));
98 writel(0x3, SIUL2_MSCRn(902));
99
100 /* PK7 pad: uSDHC CMD */
101 writel(SIUL2_USDHC_PAD_CTRL_CMD, SIUL2_MSCRn(151));
102 writel(0x3, SIUL2_MSCRn(901));
103
104 /* PK8 pad: uSDHC DAT0 */
105 writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(152));
106 writel(0x3, SIUL2_MSCRn(903));
107
108 /* PK9 pad: uSDHC DAT1 */
109 writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(153));
110 writel(0x3, SIUL2_MSCRn(904));
111
112 /* PK10 pad: uSDHC DAT2 */
113 writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(154));
114 writel(0x3, SIUL2_MSCRn(905));
115
116 /* PK11 pad: uSDHC DAT3 */
117 writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(155));
118 writel(0x3, SIUL2_MSCRn(906));
119
120 /* PK15 pad: uSDHC DAT4 */
121 writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(159));
122 writel(0x3, SIUL2_MSCRn(907));
123
124 /* PL0 pad: uSDHC DAT5 */
125 writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(160));
126 writel(0x3, SIUL2_MSCRn(908));
127
128 /* PL1 pad: uSDHC DAT6 */
129 writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(161));
130 writel(0x3, SIUL2_MSCRn(909));
131
132 /* PL2 pad: uSDHC DAT7 */
133 writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(162));
134 writel(0x3, SIUL2_MSCRn(910));
135
136 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
137 }
138 #endif
139
mscm_init(void)140 static void mscm_init(void)
141 {
142 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;
143 int i;
144
145 for (i = 0; i < MSCM_IRSPRC_NUM; i++)
146 writew(MSCM_IRSPRC_CPn_EN, &mscmir->irsprc[i]);
147 }
148
board_phy_config(struct phy_device * phydev)149 int board_phy_config(struct phy_device *phydev)
150 {
151 if (phydev->drv->config)
152 phydev->drv->config(phydev);
153
154 return 0;
155 }
156
board_early_init_f(void)157 int board_early_init_f(void)
158 {
159 clock_init();
160 mscm_init();
161
162 setup_iomux_uart();
163 setup_iomux_enet();
164 setup_iomux_i2c();
165 #ifdef CONFIG_SYS_USE_NAND
166 setup_iomux_nfc();
167 #endif
168 return 0;
169 }
170
board_init(void)171 int board_init(void)
172 {
173 /* address of boot parameters */
174 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
175
176 return 0;
177 }
178
checkboard(void)179 int checkboard(void)
180 {
181 puts("Board: s32v234evb\n");
182
183 return 0;
184 }
185