1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 *
5 * Shengzhou Liu <Shengzhou.Liu@freescale.com>
6 */
7
8 #include <common.h>
9 #include <command.h>
10 #include <fdt_support.h>
11 #include <net.h>
12 #include <netdev.h>
13 #include <asm/mmu.h>
14 #include <asm/processor.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_law.h>
17 #include <asm/fsl_serdes.h>
18 #include <asm/fsl_portals.h>
19 #include <asm/fsl_liodn.h>
20 #include <malloc.h>
21 #include <fm_eth.h>
22 #include <fsl_mdio.h>
23 #include <miiphy.h>
24 #include <phy.h>
25 #include <fsl_dtsec.h>
26 #include <asm/fsl_serdes.h>
27 #include "../common/fman.h"
28
board_eth_init(struct bd_info * bis)29 int board_eth_init(struct bd_info *bis)
30 {
31 #if defined(CONFIG_FMAN_ENET)
32 int i, interface;
33 struct memac_mdio_info dtsec_mdio_info;
34 struct memac_mdio_info tgec_mdio_info;
35 struct mii_dev *dev;
36 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
37 u32 srds_s1;
38
39 srds_s1 = in_be32(&gur->rcwsr[4]) &
40 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
41 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
42
43 dtsec_mdio_info.regs =
44 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
45
46 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
47
48 /* Register the 1G MDIO bus */
49 fm_memac_mdio_init(bis, &dtsec_mdio_info);
50
51 tgec_mdio_info.regs =
52 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
53 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
54
55 /* Register the 10G MDIO bus */
56 fm_memac_mdio_init(bis, &tgec_mdio_info);
57
58 /* Set the on-board RGMII PHY address */
59 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
60
61 switch (srds_s1) {
62 #ifdef CONFIG_TARGET_T1024RDB
63 case 0x95:
64 /* set the on-board RGMII2 PHY */
65 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
66
67 /* set 10G XFI with Aquantia AQR105 PHY */
68 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
69 break;
70 #endif
71 case 0x6a:
72 case 0x6b:
73 case 0x77:
74 case 0x135:
75 /* set the on-board 2.5G SGMII AQR105 PHY */
76 fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
77 #ifdef CONFIG_TARGET_T1023RDB
78 /* set the on-board 1G SGMII RTL8211F PHY */
79 fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
80 #endif
81 break;
82 default:
83 printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
84 srds_s1);
85 break;
86 }
87
88 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
89 interface = fm_info_get_enet_if(i);
90 switch (interface) {
91 case PHY_INTERFACE_MODE_RGMII:
92 case PHY_INTERFACE_MODE_RGMII_TXID:
93 case PHY_INTERFACE_MODE_RGMII_RXID:
94 case PHY_INTERFACE_MODE_RGMII_ID:
95 dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
96 fm_info_set_mdio(i, dev);
97 break;
98 case PHY_INTERFACE_MODE_SGMII:
99 #if defined(CONFIG_TARGET_T1023RDB)
100 dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
101 #elif defined(CONFIG_TARGET_T1024RDB)
102 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
103 #endif
104 fm_info_set_mdio(i, dev);
105 break;
106 case PHY_INTERFACE_MODE_SGMII_2500:
107 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
108 fm_info_set_mdio(i, dev);
109 break;
110 default:
111 break;
112 }
113 }
114
115 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
116 switch (fm_info_get_enet_if(i)) {
117 case PHY_INTERFACE_MODE_XGMII:
118 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
119 fm_info_set_mdio(i, dev);
120 break;
121 default:
122 break;
123 }
124 }
125
126 cpu_eth_init(bis);
127 #endif /* CONFIG_FMAN_ENET */
128
129 return pci_eth_init(bis);
130 }
131
board_ft_fman_fixup_port(void * fdt,char * compat,phys_addr_t addr,enum fm_port port,int offset)132 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
133 enum fm_port port, int offset)
134 {
135 #if defined(CONFIG_TARGET_T1024RDB)
136 if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
137 (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
138 (port == FM1_DTSEC3)) {
139 fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
140 fdt_setprop_string(fdt, offset, "phy-connection-type",
141 "sgmii-2500");
142 fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
143 }
144 #endif
145 }
146
fdt_fixup_board_enet(void * fdt)147 void fdt_fixup_board_enet(void *fdt)
148 {
149 }
150