1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2021 Gateworks Corporation
4 */
5
6 #include <common.h>
7 #include <cpu_func.h>
8 #include <hang.h>
9 #include <i2c.h>
10 #include <image.h>
11 #include <init.h>
12 #include <log.h>
13 #include <spl.h>
14 #include <asm/io.h>
15 #include <asm/mach-imx/gpio.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/imx8mm_pins.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/mach-imx/boot_mode.h>
21 #include <asm/arch/ddr.h>
22 #include <asm-generic/gpio.h>
23
24 #include <dm/uclass.h>
25 #include <dm/device.h>
26 #include <dm/uclass-internal.h>
27 #include <dm/device-internal.h>
28
29 #include <power/mp5416.h>
30
31 #include "gsc.h"
32 #include "lpddr4_timing.h"
33
34 #define PCIE_RSTN IMX_GPIO_NR(4, 6)
35
36 DECLARE_GLOBAL_DATA_PTR;
37
spl_dram_init(int size)38 static void spl_dram_init(int size)
39 {
40 struct dram_timing_info *dram_timing;
41
42 switch (size) {
43 case 1:
44 dram_timing = &dram_timing_1gb;
45 break;
46 case 4:
47 dram_timing = &dram_timing_4gb;
48 break;
49 default:
50 printf("Unknown DDR configuration: %d GiB\n", size);
51 dram_timing = &dram_timing_1gb;
52 size = 1;
53 }
54
55 printf("DRAM : LPDDR4 %d GiB\n", size);
56 ddr_init(dram_timing);
57 writel(size, M4_BOOTROM_BASE_ADDR);
58 }
59
60 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
61 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
62
63 static iomux_v3_cfg_t const uart_pads[] = {
64 IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
65 IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
66 };
67
68 static iomux_v3_cfg_t const wdog_pads[] = {
69 IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
70 };
71
board_early_init_f(void)72 int board_early_init_f(void)
73 {
74 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
75
76 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
77
78 set_wdog_reset(wdog);
79
80 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
81
82 return 0;
83 }
84
85 /*
86 * Model specific PMIC adjustments necessary prior to DRAM init
87 *
88 * Note that we can not use pmic dm drivers here as we have a generic
89 * venice dt that does not have board-specific pmic's defined.
90 *
91 * Instead we must use dm_i2c.
92 */
power_init_board(void)93 static int power_init_board(void)
94 {
95 const char *model = gsc_get_model();
96 struct udevice *bus;
97 struct udevice *dev;
98 int ret;
99
100 if ((!strncmp(model, "GW71", 4)) ||
101 (!strncmp(model, "GW72", 4)) ||
102 (!strncmp(model, "GW73", 4))) {
103 ret = uclass_get_device_by_name(UCLASS_I2C, "i2c@30a20000", &bus);
104 if (ret) {
105 printf("PMIC : failed I2C1 probe: %d\n", ret);
106 return ret;
107 }
108 ret = dm_i2c_probe(bus, 0x69, 0, &dev);
109 if (ret) {
110 printf("PMIC : failed probe: %d\n", ret);
111 return ret;
112 }
113 puts("PMIC : MP5416\n");
114
115 /* set VDD_ARM SW3 to 0.92V for 1.6GHz */
116 dm_i2c_reg_write(dev, MP5416_VSET_SW3,
117 BIT(7) | MP5416_VSET_SW3_SVAL(920000));
118 }
119
120 return 0;
121 }
122
board_init_f(ulong dummy)123 void board_init_f(ulong dummy)
124 {
125 struct udevice *dev;
126 int ret;
127 int dram_sz;
128
129 arch_cpu_init();
130
131 init_uart_clk(1);
132
133 board_early_init_f();
134
135 timer_init();
136
137 preloader_console_init();
138
139 /* Clear the BSS. */
140 memset(__bss_start, 0, __bss_end - __bss_start);
141
142 ret = spl_early_init();
143 if (ret) {
144 debug("spl_early_init() failed: %d\n", ret);
145 hang();
146 }
147
148 ret = uclass_get_device_by_name(UCLASS_CLK,
149 "clock-controller@30380000",
150 &dev);
151 if (ret < 0) {
152 printf("Failed to find clock node. Check device tree\n");
153 hang();
154 }
155
156 enable_tzc380();
157
158 /* need to hold PCIe switch in reset otherwise it can lock i2c bus EEPROM is on */
159 gpio_request(PCIE_RSTN, "perst#");
160 gpio_direction_output(PCIE_RSTN, 0);
161
162 /* GSC */
163 dram_sz = gsc_init(0);
164
165 /* PMIC */
166 power_init_board();
167
168 /* DDR initialization */
169 spl_dram_init(dram_sz);
170
171 board_init_r(NULL, 0);
172 }
173
174 /* determine prioritized order of boot devices to load U-Boot from */
board_boot_order(u32 * spl_boot_list)175 void board_boot_order(u32 *spl_boot_list)
176 {
177 /*
178 * If the SPL was loaded via serial loader, we try to get
179 * U-Boot proper via USB SDP.
180 */
181 if (spl_boot_device() == BOOT_DEVICE_BOARD)
182 spl_boot_list[0] = BOOT_DEVICE_BOARD;
183
184 /* we have only eMMC in default venice dt */
185 spl_boot_list[0] = BOOT_DEVICE_MMC1;
186 }
187
188 /* return boot device based on where the SPL was loaded from */
spl_board_boot_device(enum boot_device boot_dev_spl)189 int spl_board_boot_device(enum boot_device boot_dev_spl)
190 {
191 switch (boot_dev_spl) {
192 case USB_BOOT:
193 return BOOT_DEVICE_BOARD;
194 /* SDHC2 */
195 case SD2_BOOT:
196 case MMC2_BOOT:
197 return BOOT_DEVICE_MMC1;
198 /* SDHC3 */
199 case SD3_BOOT:
200 case MMC3_BOOT:
201 return BOOT_DEVICE_MMC2;
202 default:
203 return BOOT_DEVICE_NONE;
204 }
205 }
206