1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2014
4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
5 */
6
7 #ifdef CONFIG_GDSYS_LEGACY_DRIVERS
8
9 #include <common.h>
10 #include <i2c.h>
11
12 #define ADV7611_I2C_ADDR 0x4c
13 #define ADV7611_RDINFO 0x2051
14
15 /*
16 * ADV7611 I2C Addresses in u-boot notation
17 */
18 enum {
19 CP_I2C_ADDR = 0x22,
20 DPLL_I2C_ADDR = 0x26,
21 KSV_I2C_ADDR = 0x32,
22 HDMI_I2C_ADDR = 0x34,
23 EDID_I2C_ADDR = 0x36,
24 INFOFRAME_I2C_ADDR = 0x3e,
25 CEC_I2C_ADDR = 0x40,
26 IO_I2C_ADDR = ADV7611_I2C_ADDR,
27 };
28
29 /*
30 * Global Control Registers
31 */
32 enum {
33 IO_RD_INFO_MSB = 0xea,
34 IO_RD_INFO_LSB = 0xeb,
35 IO_CEC_ADDR = 0xf4,
36 IO_INFOFRAME_ADDR = 0xf5,
37 IO_DPLL_ADDR = 0xf8,
38 IO_KSV_ADDR = 0xf9,
39 IO_EDID_ADDR = 0xfa,
40 IO_HDMI_ADDR = 0xfb,
41 IO_CP_ADDR = 0xfd,
42 };
43
44 int adv7611_i2c[] = CONFIG_SYS_ADV7611_I2C;
45
adv7611_probe(unsigned int screen)46 int adv7611_probe(unsigned int screen)
47 {
48 int old_bus = i2c_get_bus_num();
49 unsigned int rd_info;
50 int res = 0;
51
52 i2c_set_bus_num(adv7611_i2c[screen]);
53
54 rd_info = (i2c_reg_read(IO_I2C_ADDR, IO_RD_INFO_MSB) << 8)
55 | i2c_reg_read(IO_I2C_ADDR, IO_RD_INFO_LSB);
56
57 if (rd_info != ADV7611_RDINFO) {
58 res = -1;
59 goto out;
60 }
61
62 /*
63 * set I2C addresses to default values
64 */
65 i2c_reg_write(IO_I2C_ADDR, IO_CEC_ADDR, CEC_I2C_ADDR << 1);
66 i2c_reg_write(IO_I2C_ADDR, IO_INFOFRAME_ADDR, INFOFRAME_I2C_ADDR << 1);
67 i2c_reg_write(IO_I2C_ADDR, IO_DPLL_ADDR, DPLL_I2C_ADDR << 1);
68 i2c_reg_write(IO_I2C_ADDR, IO_KSV_ADDR, KSV_I2C_ADDR << 1);
69 i2c_reg_write(IO_I2C_ADDR, IO_EDID_ADDR, EDID_I2C_ADDR << 1);
70 i2c_reg_write(IO_I2C_ADDR, IO_HDMI_ADDR, HDMI_I2C_ADDR << 1);
71 i2c_reg_write(IO_I2C_ADDR, IO_CP_ADDR, CP_I2C_ADDR << 1);
72
73 /*
74 * do magic initialization sequence from
75 * "ADV7611 Register Settings Recommendations Revision 1.5"
76 * with most registers undocumented
77 */
78 i2c_reg_write(CP_I2C_ADDR, 0x6c, 0x00);
79 i2c_reg_write(HDMI_I2C_ADDR, 0x9b, 0x03);
80 i2c_reg_write(HDMI_I2C_ADDR, 0x6f, 0x08);
81 i2c_reg_write(HDMI_I2C_ADDR, 0x85, 0x1f);
82 i2c_reg_write(HDMI_I2C_ADDR, 0x87, 0x70);
83 i2c_reg_write(HDMI_I2C_ADDR, 0x57, 0xda);
84 i2c_reg_write(HDMI_I2C_ADDR, 0x58, 0x01);
85 i2c_reg_write(HDMI_I2C_ADDR, 0x03, 0x98);
86 i2c_reg_write(HDMI_I2C_ADDR, 0x4c, 0x44);
87
88 /*
89 * IO_REG_02, default 0xf0
90 *
91 * INP_COLOR_SPACE (IO, Address 0x02[7:4])
92 * default: 0b1111 auto
93 * set to : 0b0001 force RGB (range 0 to 255) input
94 *
95 * RGB_OUT (IO, Address 0x02[1])
96 * default: 0 YPbPr color space output
97 * set to : 1 RGB color space output
98 */
99 i2c_reg_write(IO_I2C_ADDR, 0x02, 0x12);
100
101 /*
102 * IO_REG_03, default 0x00
103 *
104 * OP_FORMAT_SEL (IO, Address 0x03[7:0])
105 * default: 0x00 8-bit SDR ITU-656 mode
106 * set to : 0x40 24-bit 4:4:4 SDR mode
107 */
108 i2c_reg_write(IO_I2C_ADDR, 0x03, 0x40);
109
110 /*
111 * IO_REG_05, default 0x2c
112 *
113 * AVCODE_INSERT_EN (IO, Address 0x05[2])
114 * default: 1 insert AV codes into data stream
115 * set to : 0 do not insert AV codes into data stream
116 */
117 i2c_reg_write(IO_I2C_ADDR, 0x05, 0x28);
118
119 /*
120 * IO_REG_0C, default 0x62
121 *
122 * POWER_DOWN (IO, Address 0x0C[5])
123 * default: 1 chip is powered down
124 * set to : 0 chip is operational
125 */
126 i2c_reg_write(IO_I2C_ADDR, 0x0c, 0x42);
127
128 /*
129 * IO_REG_15, default 0xbe
130 *
131 * TRI_SYNCS (IO, Address 0x15[3)
132 * TRI_LLC (IO, Address 0x15[2])
133 * TRI_PIX (IO, Address 0x15[1])
134 * default: 1 video output pins are tristate
135 * set to : 0 video output pins are active
136 */
137 i2c_reg_write(IO_I2C_ADDR, 0x15, 0xb0);
138
139 /*
140 * HDMI_REGISTER_02H, default 0xff
141 *
142 * CLOCK_TERMA_DISABLE (HDMI, Address 0x83[0])
143 * default: 1 disable termination
144 * set to : 0 enable termination
145 * Future options are:
146 * - use the chips automatic termination control
147 * - set this manually on cable detect
148 * but at the moment this seems a safe default.
149 */
150 i2c_reg_write(HDMI_I2C_ADDR, 0x83, 0xfe);
151
152 /*
153 * HDMI_CP_CNTRL_1, default 0x01
154 *
155 * HDMI_FRUN_EN (CP, Address 0xBA[0])
156 * default: 1 Enable the free run feature in HDMI mode
157 * set to : 0 Disable the free run feature in HDMI mode
158 */
159 i2c_reg_write(CP_I2C_ADDR, 0xba, 0x00);
160
161 /*
162 * INT1_CONFIGURATION, default 0x20
163 *
164 * INTRQ_DUR_SEL[1:0] (IO, Address 0x40[7:6])
165 * default: 00 Interrupt signal is active for 4 Xtal periods
166 * set to : 11 Active until cleared
167 *
168 * INTRQ_OP_SEL[1:0] (IO, Address 0x40[1:0])
169 * default: 00 Open drain
170 * set to : 10 Drives high when active
171 */
172 i2c_reg_write(IO_I2C_ADDR, 0x40, 0xc2);
173
174 out:
175 i2c_set_bus_num(old_bus);
176
177 return res;
178 }
179
180 #endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
181