1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2012
4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
5 */
6
7 #ifdef CONFIG_GDSYS_LEGACY_DRIVERS
8
9 #include <common.h>
10 #include <asm/io.h>
11 #include <errno.h>
12
13 #include <gdsys_fpga.h>
14 #include <linux/delay.h>
15
16 enum {
17 MCINT_SLAVE_LINK_CHANGED_EV = 1 << 7,
18 MCINT_TX_ERROR_EV = 1 << 9,
19 MCINT_TX_BUFFER_FREE = 1 << 10,
20 MCINT_TX_PACKET_TRANSMITTED_EV = 1 << 11,
21 MCINT_RX_ERROR_EV = 1 << 13,
22 MCINT_RX_CONTENT_AVAILABLE = 1 << 14,
23 MCINT_RX_PACKET_RECEIVED_EV = 1 << 15,
24 };
25
mclink_probe(void)26 int mclink_probe(void)
27 {
28 unsigned int k;
29 int slaves = 0;
30
31 for (k = 0; k < CONFIG_SYS_MCLINK_MAX; ++k) {
32 int timeout = 0;
33 unsigned int ctr = 0;
34 u16 mc_status;
35
36 FPGA_GET_REG(k, mc_status, &mc_status);
37
38 if (!(mc_status & (1 << 15)))
39 break;
40
41 FPGA_SET_REG(k, mc_control, 0x8000);
42
43 FPGA_GET_REG(k, mc_status, &mc_status);
44 while (!(mc_status & (1 << 14))) {
45 udelay(100);
46 if (ctr++ > 500) {
47 timeout = 1;
48 break;
49 }
50 FPGA_GET_REG(k, mc_status, &mc_status);
51 }
52 if (timeout)
53 break;
54
55 printf("waited %d us for mclink %d to come up\n", ctr * 100, k);
56
57 slaves++;
58 }
59
60 return slaves;
61 }
62
mclink_send(u8 slave,u16 addr,u16 data)63 int mclink_send(u8 slave, u16 addr, u16 data)
64 {
65 unsigned int ctr = 0;
66 u16 int_status;
67 u16 rx_cmd_status;
68 u16 rx_cmd;
69
70 /* reset interrupt status */
71 FPGA_GET_REG(0, mc_int, &int_status);
72 FPGA_SET_REG(0, mc_int, int_status);
73
74 /* send */
75 FPGA_SET_REG(0, mc_tx_address, addr);
76 FPGA_SET_REG(0, mc_tx_data, data);
77 FPGA_SET_REG(0, mc_tx_cmd, (slave & 0x03) << 14);
78 FPGA_SET_REG(0, mc_control, 0x8001);
79
80 /* wait for reply */
81 FPGA_GET_REG(0, mc_int, &int_status);
82 while (!(int_status & MCINT_RX_PACKET_RECEIVED_EV)) {
83 udelay(100);
84 if (ctr++ > 3)
85 return -ETIMEDOUT;
86 FPGA_GET_REG(0, mc_int, &int_status);
87 }
88
89 FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status);
90 rx_cmd = (rx_cmd_status >> 12) & 0x03;
91 if (rx_cmd != 0)
92 printf("mclink_send: received cmd %d, expected %d\n", rx_cmd,
93 0);
94
95 return 0;
96 }
97
mclink_receive(u8 slave,u16 addr,u16 * data)98 int mclink_receive(u8 slave, u16 addr, u16 *data)
99 {
100 u16 rx_cmd_status;
101 u16 rx_cmd;
102 u16 int_status;
103 unsigned int ctr = 0;
104
105 /* send read request */
106 FPGA_SET_REG(0, mc_tx_address, addr);
107 FPGA_SET_REG(0, mc_tx_cmd,
108 ((slave & 0x03) << 14) | (1 << 12) | (1 << 0));
109 FPGA_SET_REG(0, mc_control, 0x8001);
110
111
112 /* wait for reply */
113 FPGA_GET_REG(0, mc_int, &int_status);
114 while (!(int_status & MCINT_RX_CONTENT_AVAILABLE)) {
115 udelay(100);
116 if (ctr++ > 3)
117 return -ETIMEDOUT;
118 FPGA_GET_REG(0, mc_int, &int_status);
119 }
120
121 /* check reply */
122 FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status);
123 if ((rx_cmd_status >> 14) != slave) {
124 printf("mclink_receive: reply from slave %d, expected %d\n",
125 rx_cmd_status >> 14, slave);
126 return -EINVAL;
127 }
128
129 rx_cmd = (rx_cmd_status >> 12) & 0x03;
130 if (rx_cmd != 1) {
131 printf("mclink_send: received cmd %d, expected %d\n",
132 rx_cmd, 1);
133 return -EIO;
134 }
135
136 FPGA_GET_REG(0, mc_rx_data, data);
137
138 return 0;
139 }
140
141 #endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
142