1 /*
2 * (C) Copyright 2013
3 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include <common.h>
25 #include <command.h>
26 #include <env.h>
27 #include <image.h>
28 #include <init.h>
29 #include <net.h>
30 #include <pci.h>
31 #include <asm/processor.h>
32 #include <asm/mmu.h>
33 #include <asm/cache.h>
34 #include <asm/immap_85xx.h>
35 #include <asm/fsl_pci.h>
36 #include <fsl_ddr_sdram.h>
37 #include <asm/fsl_serdes.h>
38 #include <asm/io.h>
39 #include <linux/delay.h>
40 #include <linux/libfdt.h>
41 #include <fdt_support.h>
42 #include <fsl_mdio.h>
43 #include <tsec.h>
44 #include <asm/fsl_law.h>
45 #include <netdev.h>
46 #include <i2c.h>
47 #include <pca9698.h>
48 #include <watchdog.h>
49 #include "../common/dp501.h"
50 #include "controlcenterd-id.h"
51
52 enum {
53 HWVER_100 = 0,
54 HWVER_110 = 1,
55 HWVER_120 = 2,
56 };
57
58 struct ihs_fpga {
59 u32 reflection_low; /* 0x0000 */
60 u32 versions; /* 0x0004 */
61 u32 fpga_version; /* 0x0008 */
62 u32 fpga_features; /* 0x000c */
63 u32 reserved[4]; /* 0x0010 */
64 u32 control; /* 0x0020 */
65 };
66
67 #ifndef CONFIG_TRAILBLAZER
68 static struct pci_device_id hydra_supported[] = {
69 { 0x6d5e, 0xcdc0 },
70 {}
71 };
72
73 static void hydra_initialize(void);
74 #endif
75
board_early_init_f(void)76 int board_early_init_f(void)
77 {
78 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
79 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
80
81 /* Reset eLBC_DIU and SPI_eLBC in case we are booting from SD */
82 clrsetbits_be32(&gur->pmuxcr, 0x00600000, 0x80000000);
83
84 /* Set pmuxcr to allow both i2c1 and i2c2 */
85 setbits_be32(&gur->pmuxcr, 0x00001000);
86
87 /* Set pmuxcr to enable GPIO 3_11-3_13 */
88 setbits_be32(&gur->pmuxcr, 0x00000010);
89
90 /* Set pmuxcr to enable GPIO 2_31,3_9+10 */
91 setbits_be32(&gur->pmuxcr, 0x00000020);
92
93 /* Set pmuxcr to enable GPIO 2_28-2_30 */
94 setbits_be32(&gur->pmuxcr, 0x000000c0);
95
96 /* Set pmuxcr to enable GPIO 3_20-3_22 */
97 setbits_be32(&gur->pmuxcr2, 0x03000000);
98
99 /* Set pmuxcr to enable IRQ0-2 */
100 clrbits_be32(&gur->pmuxcr, 0x00000300);
101
102 /* Set pmuxcr to disable IRQ3-11 */
103 setbits_be32(&gur->pmuxcr, 0x000000F0);
104
105 /* Read back the register to synchronize the write. */
106 in_be32(&gur->pmuxcr);
107
108 /* Set the pin muxing to enable ETSEC2. */
109 clrbits_be32(&gur->pmuxcr2, 0x001F8000);
110
111 #ifdef CONFIG_TRAILBLAZER
112 /*
113 * GPIO3_10 SPERRTRIGGER
114 */
115 setbits_be32(&pgpio->gpdir, 0x00200000);
116 clrbits_be32(&pgpio->gpdat, 0x00200000);
117 udelay(100);
118 setbits_be32(&pgpio->gpdat, 0x00200000);
119 udelay(100);
120 clrbits_be32(&pgpio->gpdat, 0x00200000);
121 #endif
122
123 /*
124 * GPIO3_11 CPU-TO-FPGA-RESET#
125 */
126 setbits_be32(&pgpio->gpdir, 0x00100000);
127 clrbits_be32(&pgpio->gpdat, 0x00100000);
128
129 /*
130 * GPIO3_21 CPU-STATUS-WATCHDOG-TRIGGER#
131 */
132 setbits_be32(&pgpio->gpdir, 0x00000400);
133
134 return 0;
135 }
136
checkboard(void)137 int checkboard(void)
138 {
139 printf("Board: ControlCenter DIGITAL\n");
140
141 return 0;
142 }
143
misc_init_r(void)144 int misc_init_r(void)
145 {
146 return 0;
147 }
148
149 /*
150 * A list of PCI and SATA slots
151 */
152 enum slot_id {
153 SLOT_PCIE1 = 1,
154 SLOT_PCIE2,
155 SLOT_PCIE3,
156 SLOT_PCIE4,
157 SLOT_PCIE5,
158 SLOT_SATA1,
159 SLOT_SATA2
160 };
161
162 /*
163 * This array maps the slot identifiers to their names on the P1022DS board.
164 */
165 static const char * const slot_names[] = {
166 [SLOT_PCIE1] = "Slot 1",
167 [SLOT_PCIE2] = "Slot 2",
168 [SLOT_PCIE3] = "Slot 3",
169 [SLOT_PCIE4] = "Slot 4",
170 [SLOT_PCIE5] = "Mini-PCIe",
171 [SLOT_SATA1] = "SATA 1",
172 [SLOT_SATA2] = "SATA 2",
173 };
174
175 /*
176 * This array maps a given SERDES configuration and SERDES device to the PCI or
177 * SATA slot that it connects to. This mapping is hard-coded in the FPGA.
178 */
179 static u8 serdes_dev_slot[][SATA2 + 1] = {
180 [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
181 [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
182 [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
183 [PCIE2] = SLOT_PCIE5 },
184 [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
185 [PCIE2] = SLOT_PCIE3,
186 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
187 [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
188 [PCIE2] = SLOT_PCIE3 },
189 [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
190 [PCIE2] = SLOT_PCIE3,
191 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
192 [0x1c] = { [PCIE1] = SLOT_PCIE1,
193 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
194 [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
195 [0x1f] = { [PCIE1] = SLOT_PCIE1 },
196 };
197
198
199 /*
200 * Returns the name of the slot to which the PCIe or SATA controller is
201 * connected
202 */
board_serdes_name(enum srds_prtcl device)203 const char *board_serdes_name(enum srds_prtcl device)
204 {
205 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
206 u32 pordevsr = in_be32(&gur->pordevsr);
207 unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
208 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
209 enum slot_id slot = serdes_dev_slot[srds_cfg][device];
210 const char *name = slot_names[slot];
211
212 if (name)
213 return name;
214 else
215 return "Nothing";
216 }
217
hw_watchdog_reset(void)218 void hw_watchdog_reset(void)
219 {
220 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
221
222 clrbits_be32(&pgpio->gpdat, 0x00000400);
223 setbits_be32(&pgpio->gpdat, 0x00000400);
224 }
225
226 #ifdef CONFIG_TRAILBLAZER
do_bootd(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])227 int do_bootd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
228 {
229 return run_command(env_get("bootcmd"), flag);
230 }
231
board_early_init_r(void)232 int board_early_init_r(void)
233 {
234 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
235
236 /*
237 * GPIO3_12 PPC_SYSTEMREADY#
238 */
239 setbits_be32(&pgpio->gpdir, 0x00080000);
240 setbits_be32(&pgpio->gpodr, 0x00080000);
241 clrbits_be32(&pgpio->gpdat, 0x00080000);
242
243 return ccdm_compute_self_hash();
244 }
245
last_stage_init(void)246 int last_stage_init(void)
247 {
248 startup_ccdm_id_module();
249 return 0;
250 }
251
252 #else
pci_init_board(void)253 void pci_init_board(void)
254 {
255 fsl_pcie_init_board(0);
256
257 hydra_initialize();
258 }
259
board_early_init_r(void)260 int board_early_init_r(void)
261 {
262 unsigned int k = 0;
263 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
264
265 /* wait for FPGA configuration to finish */
266 while (!pca9698_get_value(0x22, 11) && (k++ < 30))
267 udelay(100000);
268
269 if (k > 30) {
270 puts("FPGA configuration timed out.\n");
271 } else {
272 /* clear FPGA reset */
273 udelay(1000);
274 setbits_be32(&pgpio->gpdat, 0x00100000);
275 }
276
277 /* give time for PCIe link training */
278 udelay(100000);
279
280 /*
281 * GPIO3_12 PPC_SYSTEMREADY#
282 */
283 setbits_be32(&pgpio->gpdir, 0x00080000);
284 setbits_be32(&pgpio->gpodr, 0x00080000);
285 clrbits_be32(&pgpio->gpdat, 0x00080000);
286
287 return 0;
288 }
289
last_stage_init(void)290 int last_stage_init(void)
291 {
292 /* Turn on Parade DP501 */
293 pca9698_direction_output(0x22, 7, 1);
294 udelay(500000);
295
296 dp501_powerup(0x08);
297
298 startup_ccdm_id_module();
299
300 return 0;
301 }
302
303 /*
304 * Initialize on-board and/or PCI Ethernet devices
305 *
306 * Returns:
307 * <0, error
308 * 0, no ethernet devices found
309 * >0, number of ethernet devices initialized
310 */
board_eth_init(struct bd_info * bis)311 int board_eth_init(struct bd_info *bis)
312 {
313 struct fsl_pq_mdio_info mdio_info;
314 struct tsec_info_struct tsec_info[2];
315 unsigned int num = 0;
316
317 #ifdef CONFIG_TSEC1
318 SET_STD_TSEC_INFO(tsec_info[num], 1);
319 num++;
320 #endif
321 #ifdef CONFIG_TSEC2
322 SET_STD_TSEC_INFO(tsec_info[num], 2);
323 num++;
324 #endif
325
326 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
327 mdio_info.name = DEFAULT_MII_NAME;
328 fsl_pq_mdio_init(bis, &mdio_info);
329
330 return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
331 }
332
333 #ifdef CONFIG_OF_BOARD_SETUP
ft_board_setup(void * blob,struct bd_info * bd)334 int ft_board_setup(void *blob, struct bd_info *bd)
335 {
336 phys_addr_t base;
337 phys_size_t size;
338
339 ft_cpu_setup(blob, bd);
340
341 base = env_get_bootm_low();
342 size = env_get_bootm_size();
343
344 fdt_fixup_memory(blob, (u64)base, (u64)size);
345
346 #ifdef CONFIG_HAS_FSL_DR_USB
347 fsl_fdt_fixup_dr_usb(blob, bd);
348 #endif
349
350 FT_FSL_PCI_SETUP;
351
352 return 0;
353 }
354 #endif
355
hydra_initialize(void)356 static void hydra_initialize(void)
357 {
358 unsigned int i;
359 pci_dev_t devno;
360
361 /* Find and probe all the matching PCI devices */
362 for (i = 0; (devno = pci_find_devices(hydra_supported, i)) >= 0; i++) {
363 u32 val;
364 struct ihs_fpga *fpga;
365 u32 versions;
366 u32 fpga_version;
367 u32 fpga_features;
368
369 unsigned hardware_version;
370 unsigned feature_uart_channels;
371 unsigned feature_sb_channels;
372
373 /* Try to enable I/O accesses and bus-mastering */
374 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
375 pci_write_config_dword(devno, PCI_COMMAND, val);
376
377 /* Make sure it worked */
378 pci_read_config_dword(devno, PCI_COMMAND, &val);
379 if (!(val & PCI_COMMAND_MEMORY)) {
380 puts("Can't enable I/O memory\n");
381 continue;
382 }
383 if (!(val & PCI_COMMAND_MASTER)) {
384 puts("Can't enable bus-mastering\n");
385 continue;
386 }
387
388 /* read FPGA details */
389 fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
390 PCI_REGION_MEM);
391
392 /* disable sideband clocks */
393 writel(1, &fpga->control);
394
395 versions = readl(&fpga->versions);
396 fpga_version = readl(&fpga->fpga_version);
397 fpga_features = readl(&fpga->fpga_features);
398
399 hardware_version = versions & 0xf;
400 feature_uart_channels = (fpga_features >> 6) & 0x1f;
401 feature_sb_channels = fpga_features & 0x1f;
402
403 printf("FPGA%d: ", i);
404
405 switch (hardware_version) {
406 case HWVER_100:
407 printf("HW-Ver 1.00\n");
408 break;
409
410 case HWVER_110:
411 printf("HW-Ver 1.10\n");
412 break;
413
414 case HWVER_120:
415 printf("HW-Ver 1.20\n");
416 break;
417
418 default:
419 printf("HW-Ver %d(not supported)\n",
420 hardware_version);
421 break;
422 }
423
424 printf(" FPGA V %d.%02d, features:",
425 fpga_version / 100, fpga_version % 100);
426
427 printf(" %d uart channel(s)", feature_uart_channels);
428 printf(" %d sideband channel(s)\n", feature_sb_channels);
429 }
430 }
431 #endif
432