1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * Authors: Timur Tabi <timur@freescale.com>
5 *
6 * FSL DIU Framebuffer driver
7 */
8
9 #include <common.h>
10 #include <clock_legacy.h>
11 #include <command.h>
12 #include <log.h>
13 #include <linux/ctype.h>
14 #include <asm/io.h>
15 #include <stdio_dev.h>
16 #include <video_fb.h>
17 #include <fsl_diu_fb.h>
18
19 #define PMUXCR_ELBCDIU_MASK 0xc0000000
20 #define PMUXCR_ELBCDIU_NOR16 0x80000000
21 #define PMUXCR_ELBCDIU_DIU 0x40000000
22
23 /*
24 * DIU Area Descriptor
25 *
26 * Note that we need to byte-swap the value before it's written to the AD
27 * register. So even though the registers don't look like they're in the same
28 * bit positions as they are on the MPC8610, the same value is written to the
29 * AD register on the MPC8610 and on the P1022.
30 */
31 #define AD_BYTE_F 0x10000000
32 #define AD_ALPHA_C_SHIFT 25
33 #define AD_BLUE_C_SHIFT 23
34 #define AD_GREEN_C_SHIFT 21
35 #define AD_RED_C_SHIFT 19
36 #define AD_PIXEL_S_SHIFT 16
37 #define AD_COMP_3_SHIFT 12
38 #define AD_COMP_2_SHIFT 8
39 #define AD_COMP_1_SHIFT 4
40 #define AD_COMP_0_SHIFT 0
41
42 /*
43 * Variables used by the DIU/LBC switching code. It's safe to makes these
44 * global, because the DIU requires DDR, so we'll only run this code after
45 * relocation.
46 */
47 static u32 pmuxcr;
48
diu_set_pixel_clock(unsigned int pixclock)49 void diu_set_pixel_clock(unsigned int pixclock)
50 {
51 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
52 unsigned long speed_ccb, temp;
53 u32 pixval;
54
55 speed_ccb = get_bus_freq(0);
56 temp = 1000000000 / pixclock;
57 temp *= 1000;
58 pixval = speed_ccb / temp;
59 debug("DIU pixval = %u\n", pixval);
60
61 /* Modify PXCLK in GUTS CLKDVDR */
62 temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
63 out_be32(&gur->clkdvdr, temp); /* turn off clock */
64 out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
65 }
66
platform_diu_init(unsigned int xres,unsigned int yres,const char * port)67 int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
68 {
69 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
70 u32 pixel_format;
71
72 pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
73 (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
74 (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
75 (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
76 (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
77
78 printf("DIU: Switching to %ux%u\n", xres, yres);
79
80 /* Set PMUXCR to switch the muxed pins from the LBC to the DIU */
81 clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);
82 pmuxcr = in_be32(&gur->pmuxcr);
83
84 return fsl_diu_init(xres, yres, pixel_format, 0);
85 }
86