1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * USB armory MkI board initialization
4 * http://inversepath.com/usbarmory
5 *
6 * Copyright (C) 2015, Inverse Path
7 * Andrej Rosano <andrej@inversepath.com>
8 */
9
10 #include <common.h>
11 #include <command.h>
12 #include <fs.h>
13 #include <init.h>
14 #include <asm/global_data.h>
15 #include <asm/io.h>
16 #include <asm/arch/imx-regs.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/crm_regs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/iomux-mx53.h>
21 #include <linux/delay.h>
22 #include <linux/errno.h>
23 #include <i2c.h>
24 #include <mmc.h>
25 #include <fsl_esdhc_imx.h>
26 #include <asm/gpio.h>
27
28 DECLARE_GLOBAL_DATA_PTR;
29
get_board_rev(void)30 u32 get_board_rev(void)
31 {
32 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
33 struct fuse_bank *bank = &iim->bank[0];
34 struct fuse_bank0_regs *fuse =
35 (struct fuse_bank0_regs *)bank->fuse_regs;
36
37 int rev = readl(&fuse->gp[6]);
38
39 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
40 }
41
42 struct fsl_esdhc_cfg esdhc_cfg[1] = {
43 {MMC_SDHC1_BASE_ADDR}
44 };
45
board_mmc_getcd(struct mmc * mmc)46 int board_mmc_getcd(struct mmc *mmc)
47 {
48 /* CD not present */
49 return 1;
50 }
51
board_mmc_init(struct bd_info * bis)52 int board_mmc_init(struct bd_info *bis)
53 {
54 int ret = 0;
55
56 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
57 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
58
59 return ret;
60 }
61
62 #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
63 PAD_CTL_PUS_100K_UP)
64 #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
65 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
66 #define PAD_CTRL_UP PAD_CTL_PUS_100K_UP
67 #define PAD_CTRL_GND PAD_CTL_PUS_100K_DOWN
68
setup_iomux_sd(void)69 static void setup_iomux_sd(void)
70 {
71 static const iomux_v3_cfg_t pads[] = {
72 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
73 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, MX53_SDHC_PAD_CTRL),
74 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
75 MX53_SDHC_PAD_CTRL),
76 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
77 MX53_SDHC_PAD_CTRL),
78 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
79 MX53_SDHC_PAD_CTRL),
80 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
81 MX53_SDHC_PAD_CTRL),
82 MX53_PAD_EIM_DA13__GPIO3_13,
83 };
84
85 imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads));
86 }
87
setup_iomux_led(void)88 static void setup_iomux_led(void)
89 {
90 static const iomux_v3_cfg_t pads[] = {
91 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT6__GPIO4_27,
92 PAD_CTL_PUS_100K_DOWN),
93 };
94
95 imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads));
96 }
97
setup_iomux_i2c(void)98 static void setup_iomux_i2c(void)
99 {
100 static const iomux_v3_cfg_t pads[] = {
101 NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
102 NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
103 };
104
105 imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads));
106 }
107
setup_iomux_pinheader(void)108 static void setup_iomux_pinheader(void)
109 {
110 static const iomux_v3_cfg_t pads[] = {
111 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__GPIO5_26, PAD_CTRL_UP),
112 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__GPIO5_27, PAD_CTRL_UP),
113 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
114 MX53_UART_PAD_CTRL),
115 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
116 MX53_UART_PAD_CTRL),
117 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT12__GPIO5_30, PAD_CTRL_UP),
118 };
119
120 imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads));
121 }
122
setup_iomux_unused_boot(void)123 static void setup_iomux_unused_boot(void)
124 {
125 static const iomux_v3_cfg_t pads[] = {
126 /* Pulled-up pads */
127 NEW_PAD_CTRL(MX53_PAD_EIM_A21__GPIO2_17, PAD_CTRL_UP),
128 NEW_PAD_CTRL(MX53_PAD_EIM_DA0__GPIO3_0, PAD_CTRL_UP),
129
130 /* Grounded pads */
131 NEW_PAD_CTRL(MX53_PAD_EIM_LBA__GPIO2_27, PAD_CTRL_GND),
132 NEW_PAD_CTRL(MX53_PAD_EIM_EB0__GPIO2_28, PAD_CTRL_GND),
133 NEW_PAD_CTRL(MX53_PAD_EIM_EB1__GPIO2_29, PAD_CTRL_GND),
134 NEW_PAD_CTRL(MX53_PAD_EIM_A16__GPIO2_22, PAD_CTRL_GND),
135 NEW_PAD_CTRL(MX53_PAD_EIM_A17__GPIO2_21, PAD_CTRL_GND),
136 NEW_PAD_CTRL(MX53_PAD_EIM_A18__GPIO2_20, PAD_CTRL_GND),
137 NEW_PAD_CTRL(MX53_PAD_EIM_A19__GPIO2_19, PAD_CTRL_GND),
138 NEW_PAD_CTRL(MX53_PAD_EIM_A20__GPIO2_18, PAD_CTRL_GND),
139 NEW_PAD_CTRL(MX53_PAD_EIM_A22__GPIO2_16, PAD_CTRL_GND),
140 NEW_PAD_CTRL(MX53_PAD_EIM_DA1__GPIO3_1, PAD_CTRL_GND),
141 NEW_PAD_CTRL(MX53_PAD_EIM_DA2__GPIO3_2, PAD_CTRL_GND),
142 NEW_PAD_CTRL(MX53_PAD_EIM_DA3__GPIO3_3, PAD_CTRL_GND),
143 NEW_PAD_CTRL(MX53_PAD_EIM_DA4__GPIO3_4, PAD_CTRL_GND),
144 NEW_PAD_CTRL(MX53_PAD_EIM_DA5__GPIO3_5, PAD_CTRL_GND),
145 NEW_PAD_CTRL(MX53_PAD_EIM_DA6__GPIO3_6, PAD_CTRL_GND),
146 NEW_PAD_CTRL(MX53_PAD_EIM_DA7__GPIO3_7, PAD_CTRL_GND),
147 NEW_PAD_CTRL(MX53_PAD_EIM_DA8__GPIO3_8, PAD_CTRL_GND),
148 NEW_PAD_CTRL(MX53_PAD_EIM_DA9__GPIO3_9, PAD_CTRL_GND),
149 NEW_PAD_CTRL(MX53_PAD_EIM_DA10__GPIO3_10, PAD_CTRL_GND),
150 };
151
152 imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads));
153 }
154
setup_iomux_unused_nc(void)155 static void setup_iomux_unused_nc(void)
156 {
157 /* Out of reset values define the pin values before the
158 ROM is executed so we force all the not connected pins
159 to a known state */
160 static const iomux_v3_cfg_t pads[] = {
161 /* CONTROL PINS block */
162 NEW_PAD_CTRL(MX53_PAD_GPIO_0__GPIO1_0, PAD_CTRL_UP),
163 NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, PAD_CTRL_UP),
164 NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2, PAD_CTRL_UP),
165 NEW_PAD_CTRL(MX53_PAD_GPIO_3__GPIO1_3, PAD_CTRL_UP),
166 NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4, PAD_CTRL_UP),
167 NEW_PAD_CTRL(MX53_PAD_GPIO_5__GPIO1_5, PAD_CTRL_UP),
168 NEW_PAD_CTRL(MX53_PAD_GPIO_6__GPIO1_6, PAD_CTRL_UP),
169 NEW_PAD_CTRL(MX53_PAD_GPIO_7__GPIO1_7, PAD_CTRL_UP),
170 NEW_PAD_CTRL(MX53_PAD_GPIO_8__GPIO1_8, PAD_CTRL_UP),
171 NEW_PAD_CTRL(MX53_PAD_GPIO_9__GPIO1_9, PAD_CTRL_UP),
172 NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0, PAD_CTRL_UP),
173 NEW_PAD_CTRL(MX53_PAD_GPIO_11__GPIO4_1, PAD_CTRL_UP),
174 NEW_PAD_CTRL(MX53_PAD_GPIO_12__GPIO4_2, PAD_CTRL_UP),
175 NEW_PAD_CTRL(MX53_PAD_GPIO_13__GPIO4_3, PAD_CTRL_UP),
176 NEW_PAD_CTRL(MX53_PAD_GPIO_14__GPIO4_4, PAD_CTRL_UP),
177 NEW_PAD_CTRL(MX53_PAD_GPIO_16__GPIO7_11, PAD_CTRL_UP),
178 NEW_PAD_CTRL(MX53_PAD_GPIO_17__GPIO7_12, PAD_CTRL_UP),
179 NEW_PAD_CTRL(MX53_PAD_GPIO_18__GPIO7_13, PAD_CTRL_UP),
180 NEW_PAD_CTRL(MX53_PAD_GPIO_19__GPIO4_5, PAD_CTRL_UP),
181
182 /* EIM block */
183 NEW_PAD_CTRL(MX53_PAD_EIM_OE__GPIO2_25, PAD_CTRL_UP),
184 NEW_PAD_CTRL(MX53_PAD_EIM_WAIT__GPIO5_0, PAD_CTRL_UP),
185 /* EIM_LBA: setup_iomux_unused_boot() */
186 NEW_PAD_CTRL(MX53_PAD_EIM_RW__GPIO2_26, PAD_CTRL_UP),
187 /* EIM_EB0: setup_iomux_unused_boot() */
188 /* EIM_EB1: setup_iomux_unused_boot() */
189 NEW_PAD_CTRL(MX53_PAD_EIM_EB2__GPIO2_30, PAD_CTRL_UP),
190 NEW_PAD_CTRL(MX53_PAD_EIM_EB3__GPIO2_31, PAD_CTRL_UP),
191 NEW_PAD_CTRL(MX53_PAD_EIM_CS0__GPIO2_23, PAD_CTRL_UP),
192 NEW_PAD_CTRL(MX53_PAD_EIM_CS1__GPIO2_24, PAD_CTRL_UP),
193 /* EIM_A16: setup_iomux_unused_boot() */
194 /* EIM_A17: setup_iomux_unused_boot() */
195 /* EIM_A18: setup_iomux_unused_boot() */
196 /* EIM_A19: setup_iomux_unused_boot() */
197 /* EIM_A20: setup_iomux_unused_boot() */
198 /* EIM_A21: setup_iomux_unused_boot() */
199 /* EIM_A22: setup_iomux_unused_boot() */
200 NEW_PAD_CTRL(MX53_PAD_EIM_A23__GPIO6_6, PAD_CTRL_UP),
201 NEW_PAD_CTRL(MX53_PAD_EIM_A24__GPIO5_4, PAD_CTRL_UP),
202 NEW_PAD_CTRL(MX53_PAD_EIM_A25__GPIO5_2, PAD_CTRL_UP),
203 NEW_PAD_CTRL(MX53_PAD_EIM_D16__GPIO3_16, PAD_CTRL_UP),
204 NEW_PAD_CTRL(MX53_PAD_EIM_D17__GPIO3_17, PAD_CTRL_UP),
205 NEW_PAD_CTRL(MX53_PAD_EIM_D18__GPIO3_18, PAD_CTRL_UP),
206 NEW_PAD_CTRL(MX53_PAD_EIM_D19__GPIO3_19, PAD_CTRL_UP),
207 NEW_PAD_CTRL(MX53_PAD_EIM_D20__GPIO3_20, PAD_CTRL_UP),
208 NEW_PAD_CTRL(MX53_PAD_EIM_D21__GPIO3_21, PAD_CTRL_UP),
209 NEW_PAD_CTRL(MX53_PAD_EIM_D22__GPIO3_22, PAD_CTRL_UP),
210 NEW_PAD_CTRL(MX53_PAD_EIM_D23__GPIO3_23, PAD_CTRL_UP),
211 NEW_PAD_CTRL(MX53_PAD_EIM_D24__GPIO3_24, PAD_CTRL_UP),
212 NEW_PAD_CTRL(MX53_PAD_EIM_D25__GPIO3_25, PAD_CTRL_UP),
213 NEW_PAD_CTRL(MX53_PAD_EIM_D26__GPIO3_26, PAD_CTRL_UP),
214 NEW_PAD_CTRL(MX53_PAD_EIM_D27__GPIO3_27, PAD_CTRL_UP),
215 /* EIM_D28: setup_iomux_unused_boot() */
216 /* EIM_D29: setup_iomux_unused_boot() */
217 NEW_PAD_CTRL(MX53_PAD_EIM_D30__GPIO3_30, PAD_CTRL_UP),
218 NEW_PAD_CTRL(MX53_PAD_EIM_D31__GPIO3_31, PAD_CTRL_UP),
219 /* EIM_DA0: setup_iomux_unused_boot() */
220 /* EIM_DA1: setup_iomux_unused_boot() */
221 /* EIM_DA2: setup_iomux_unused_boot() */
222 /* EIM_DA3: setup_iomux_unused_boot() */
223 /* EIM_DA4: setup_iomux_unused_boot() */
224 /* EIM_DA5: setup_iomux_unused_boot() */
225 /* EIM_DA6: setup_iomux_unused_boot() */
226 /* EIM_DA7: setup_iomux_unused_boot() */
227 /* EIM_DA8: setup_iomux_unused_boot() */
228 /* EIM_DA9: setup_iomux_unused_boot() */
229 /* EIM_DA10: setup_iomux_unused_boot() */
230 NEW_PAD_CTRL(MX53_PAD_EIM_DA11__GPIO3_11, PAD_CTRL_UP),
231 NEW_PAD_CTRL(MX53_PAD_EIM_DA12__GPIO3_12, PAD_CTRL_UP),
232 NEW_PAD_CTRL(MX53_PAD_EIM_DA13__GPIO3_13, PAD_CTRL_UP),
233 NEW_PAD_CTRL(MX53_PAD_EIM_DA14__GPIO3_14, PAD_CTRL_UP),
234 NEW_PAD_CTRL(MX53_PAD_EIM_DA15__GPIO3_15, PAD_CTRL_UP),
235 NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__GPIO6_12, PAD_CTRL_UP),
236 NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__GPIO6_13, PAD_CTRL_UP),
237 NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__GPIO6_8, PAD_CTRL_UP),
238 NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__GPIO6_7, PAD_CTRL_UP),
239 NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__GPIO6_9, PAD_CTRL_UP),
240 NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__GPIO6_10, PAD_CTRL_UP),
241 NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__GPIO6_11, PAD_CTRL_UP),
242 NEW_PAD_CTRL(MX53_PAD_NANDF_CS1__GPIO6_14, PAD_CTRL_UP),
243 NEW_PAD_CTRL(MX53_PAD_NANDF_CS2__GPIO6_15, PAD_CTRL_UP),
244 NEW_PAD_CTRL(MX53_PAD_NANDF_CS3__GPIO6_16, PAD_CTRL_UP),
245
246 /* MISC block */
247 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__GPIO1_31, PAD_CTRL_UP),
248 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__GPIO1_22, PAD_CTRL_UP),
249 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__GPIO1_25, PAD_CTRL_UP),
250 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__GPIO1_23, PAD_CTRL_UP),
251 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__GPIO1_24, PAD_CTRL_UP),
252 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__GPIO1_28, PAD_CTRL_UP),
253 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__GPIO1_27, PAD_CTRL_UP),
254 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__GPIO1_26, PAD_CTRL_UP),
255 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__GPIO1_30, PAD_CTRL_UP),
256 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__GPIO1_29, PAD_CTRL_UP),
257 NEW_PAD_CTRL(MX53_PAD_KEY_COL0__GPIO4_6, PAD_CTRL_UP),
258 NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__GPIO4_7, PAD_CTRL_UP),
259 NEW_PAD_CTRL(MX53_PAD_KEY_COL1__GPIO4_8, PAD_CTRL_UP),
260 NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__GPIO4_9, PAD_CTRL_UP),
261 NEW_PAD_CTRL(MX53_PAD_KEY_COL2__GPIO4_10, PAD_CTRL_UP),
262 NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__GPIO4_11, PAD_CTRL_UP),
263 NEW_PAD_CTRL(MX53_PAD_KEY_COL3__GPIO4_12, PAD_CTRL_UP),
264 NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__GPIO4_13, PAD_CTRL_UP),
265 NEW_PAD_CTRL(MX53_PAD_KEY_COL4__GPIO4_14, PAD_CTRL_UP),
266 NEW_PAD_CTRL(MX53_PAD_KEY_ROW4__GPIO4_15, PAD_CTRL_UP),
267 NEW_PAD_CTRL(MX53_PAD_SD2_CMD__GPIO1_11, PAD_CTRL_UP),
268 NEW_PAD_CTRL(MX53_PAD_SD2_CLK__GPIO1_10, PAD_CTRL_UP),
269 NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__GPIO1_15, PAD_CTRL_UP),
270 NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__GPIO1_14, PAD_CTRL_UP),
271 NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__GPIO1_13, PAD_CTRL_UP),
272 NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__GPIO1_12, PAD_CTRL_UP),
273 NEW_PAD_CTRL(MX53_PAD_PATA_BUFFER_EN__GPIO7_1, PAD_CTRL_UP),
274 NEW_PAD_CTRL(MX53_PAD_PATA_CS_0__GPIO7_9, PAD_CTRL_UP),
275 NEW_PAD_CTRL(MX53_PAD_PATA_CS_1__GPIO7_10, PAD_CTRL_UP),
276 NEW_PAD_CTRL(MX53_PAD_PATA_DA_0__GPIO7_6, PAD_CTRL_UP),
277 NEW_PAD_CTRL(MX53_PAD_PATA_DA_1__GPIO7_7, PAD_CTRL_UP),
278 NEW_PAD_CTRL(MX53_PAD_PATA_DA_2__GPIO7_8, PAD_CTRL_UP),
279 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__GPIO2_0, PAD_CTRL_UP),
280 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__GPIO2_1, PAD_CTRL_UP),
281 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__GPIO2_2, PAD_CTRL_UP),
282 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__GPIO2_3, PAD_CTRL_UP),
283 NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__GPIO2_4, PAD_CTRL_UP),
284 NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__GPIO2_5, PAD_CTRL_UP),
285 NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__GPIO2_6, PAD_CTRL_UP),
286 NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__GPIO2_7, PAD_CTRL_UP),
287 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__GPIO2_8, PAD_CTRL_UP),
288 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__GPIO2_9, PAD_CTRL_UP),
289 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__GPIO2_10, PAD_CTRL_UP),
290 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__GPIO2_11, PAD_CTRL_UP),
291 NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__GPIO2_12, PAD_CTRL_UP),
292 NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__GPIO2_13, PAD_CTRL_UP),
293 NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__GPIO2_14, PAD_CTRL_UP),
294 NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__GPIO2_15, PAD_CTRL_UP),
295 NEW_PAD_CTRL(MX53_PAD_PATA_DIOR__GPIO7_3, PAD_CTRL_UP),
296 NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__GPIO6_17, PAD_CTRL_UP),
297 NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__GPIO6_18, PAD_CTRL_UP),
298 NEW_PAD_CTRL(MX53_PAD_PATA_DMARQ__GPIO7_0, PAD_CTRL_UP),
299 NEW_PAD_CTRL(MX53_PAD_PATA_INTRQ__GPIO7_2, PAD_CTRL_UP),
300 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__GPIO7_5, PAD_CTRL_UP),
301 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__GPIO7_4, PAD_CTRL_UP),
302
303 /* IPU block */
304 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT4__GPIO5_22, PAD_CTRL_UP),
305 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT5__GPIO5_23, PAD_CTRL_UP),
306 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT6__GPIO5_24, PAD_CTRL_UP),
307 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT7__GPIO5_25, PAD_CTRL_UP),
308 /* CSI0_DAT8: setup_iomux_pinheader() */
309 /* CSI0_DAT9: setup_iomux_pinheader() */
310 /* CSI0_DAT10: setup_iomux_pinheader() */
311 /* CSI0_DAT11: setup_iomux_pinheader() */
312 /* CSI0_DAT12: setup_iomux_pinheader() */
313 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT13__GPIO5_31, PAD_CTRL_UP),
314 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT14__GPIO6_0, PAD_CTRL_UP),
315 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT15__GPIO6_1, PAD_CTRL_UP),
316 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT16__GPIO6_2, PAD_CTRL_UP),
317 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT17__GPIO6_3, PAD_CTRL_UP),
318 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT18__GPIO6_4, PAD_CTRL_UP),
319 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT19__GPIO6_5, PAD_CTRL_UP),
320 NEW_PAD_CTRL(MX53_PAD_CSI0_VSYNC__GPIO5_21, PAD_CTRL_UP),
321 NEW_PAD_CTRL(MX53_PAD_CSI0_PIXCLK__GPIO5_18, PAD_CTRL_UP),
322 NEW_PAD_CTRL(MX53_PAD_CSI0_MCLK__GPIO5_19, PAD_CTRL_UP),
323 NEW_PAD_CTRL(MX53_PAD_CSI0_DATA_EN__GPIO5_20, PAD_CTRL_UP),
324 NEW_PAD_CTRL(MX53_PAD_DI0_PIN2__GPIO4_18, PAD_CTRL_UP),
325 NEW_PAD_CTRL(MX53_PAD_DI0_PIN3__GPIO4_19, PAD_CTRL_UP),
326 NEW_PAD_CTRL(MX53_PAD_DI0_PIN4__GPIO4_20, PAD_CTRL_UP),
327 NEW_PAD_CTRL(MX53_PAD_DI0_PIN15__GPIO4_17, PAD_CTRL_UP),
328 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT0__GPIO4_21, PAD_CTRL_UP),
329 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT1__GPIO4_22, PAD_CTRL_UP),
330 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT2__GPIO4_23, PAD_CTRL_UP),
331 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT3__GPIO4_24, PAD_CTRL_UP),
332 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT4__GPIO4_25, PAD_CTRL_UP),
333 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT5__GPIO4_26, PAD_CTRL_UP),
334 /* DISP0_DAT6: setup_iomux_led() */
335 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT7__GPIO4_28, PAD_CTRL_UP),
336 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT8__GPIO4_29, PAD_CTRL_UP),
337 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT9__GPIO4_30, PAD_CTRL_UP),
338 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT10__GPIO4_31, PAD_CTRL_UP),
339 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT11__GPIO5_5, PAD_CTRL_UP),
340 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT12__GPIO5_6, PAD_CTRL_UP),
341 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT13__GPIO5_7, PAD_CTRL_UP),
342 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT14__GPIO5_8, PAD_CTRL_UP),
343 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT15__GPIO5_9, PAD_CTRL_UP),
344 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT16__GPIO5_10, PAD_CTRL_UP),
345 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT17__GPIO5_11, PAD_CTRL_UP),
346 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT18__GPIO5_12, PAD_CTRL_UP),
347 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT19__GPIO5_13, PAD_CTRL_UP),
348 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT20__GPIO5_14, PAD_CTRL_UP),
349 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT21__GPIO5_15, PAD_CTRL_UP),
350 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT22__GPIO5_16, PAD_CTRL_UP),
351 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT23__GPIO5_17, PAD_CTRL_UP),
352 NEW_PAD_CTRL(MX53_PAD_DI0_DISP_CLK__GPIO4_16, PAD_CTRL_UP),
353
354 /* LVDS block */
355 NEW_PAD_CTRL(MX53_PAD_LVDS0_TX0_P__GPIO7_30, PAD_CTRL_UP),
356 NEW_PAD_CTRL(MX53_PAD_LVDS0_TX1_P__GPIO7_28, PAD_CTRL_UP),
357 NEW_PAD_CTRL(MX53_PAD_LVDS0_TX2_P__GPIO7_26, PAD_CTRL_UP),
358 NEW_PAD_CTRL(MX53_PAD_LVDS0_TX3_P__GPIO7_22, PAD_CTRL_UP),
359 NEW_PAD_CTRL(MX53_PAD_LVDS1_TX0_P__GPIO6_30, PAD_CTRL_UP),
360 NEW_PAD_CTRL(MX53_PAD_LVDS1_TX1_P__GPIO6_28, PAD_CTRL_UP),
361 NEW_PAD_CTRL(MX53_PAD_LVDS1_TX2_P__GPIO6_24, PAD_CTRL_UP),
362 NEW_PAD_CTRL(MX53_PAD_LVDS1_TX3_P__GPIO6_22, PAD_CTRL_UP),
363 NEW_PAD_CTRL(MX53_PAD_LVDS0_CLK_P__GPIO7_24, PAD_CTRL_UP),
364 NEW_PAD_CTRL(MX53_PAD_LVDS1_CLK_P__GPIO6_26, PAD_CTRL_UP),
365 };
366
367 imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads));
368 }
369
370 #define CPU_CLOCK 800
371
set_clock(void)372 static void set_clock(void)
373 {
374 u32 ref_clk = MXC_HCLK;
375 const uint32_t cpuclk = CPU_CLOCK;
376 const uint32_t dramclk = 400;
377 int ret;
378
379 ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
380 if (ret)
381 printf("CPU: Switch CPU clock to %dMHZ failed\n", cpuclk);
382
383 ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
384 if (ret)
385 printf("CPU: Switch peripheral clock to %dMHz failed\n",
386 dramclk);
387
388 ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
389 if (ret)
390 printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk);
391 }
392
board_early_init_f(void)393 int board_early_init_f(void)
394 {
395 setup_iomux_unused_nc();
396 setup_iomux_unused_boot();
397 setup_iomux_sd();
398 setup_iomux_led();
399 setup_iomux_pinheader();
400 set_clock();
401 return 0;
402 }
403
board_init(void)404 int board_init(void)
405 {
406 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
407 setup_iomux_i2c();
408 return 0;
409 }
410
dram_init(void)411 int dram_init(void)
412 {
413 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 1 << 30);
414 return 0;
415 }
416
checkboard(void)417 int checkboard(void)
418 {
419 puts("Board: Inverse Path USB armory MkI\n");
420 return 0;
421 }
422
423 #ifndef CONFIG_CMDLINE
424 static char *ext2_argv[] = {
425 "ext2load",
426 "mmc",
427 "0:1",
428 USBARMORY_FIT_ADDR,
429 USBARMORY_FIT_PATH
430 };
431
432 static char *bootm_argv[] = {
433 "bootm",
434 USBARMORY_FIT_ADDR
435 };
436
board_run_command(const char * cmdline)437 int board_run_command(const char *cmdline)
438 {
439 printf("%s %s %s %s %s\n", ext2_argv[0], ext2_argv[1], ext2_argv[2],
440 ext2_argv[3], ext2_argv[4]);
441
442 if (do_ext2load(NULL, 0, 5, ext2_argv) != 0) {
443 udelay(5*1000*1000);
444 return 1;
445 }
446
447 printf("%s %s\n", bootm_argv[0], bootm_argv[1]);
448 do_bootm(NULL, 0, 2, bootm_argv);
449
450 return 1;
451 }
452 #endif
453