1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2016 Keymile AG
4 * Rainer Boschung <rainer.boschung@keymile.com>
5 *
6 * Copyright 2013 Freescale Semiconductor, Inc.
7 */
8
9 #include <asm/cache.h>
10 #include <asm/fsl_fdt.h>
11 #include <asm/fsl_law.h>
12 #include <asm/fsl_liodn.h>
13 #include <asm/fsl_portals.h>
14 #include <asm/fsl_serdes.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/mmu.h>
17 #include <asm/processor.h>
18 #include <fdt_support.h>
19 #include <fm_eth.h>
20 #include <hwconfig.h>
21 #include <image.h>
22 #include <linux/compiler.h>
23 #include <net.h>
24 #include <netdev.h>
25 #include <vsc9953.h>
26
27 #include "../common/common.h"
28 #include "../common/qrio.h"
29
30 DECLARE_GLOBAL_DATA_PTR;
31
32 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
33
checkboard(void)34 int checkboard(void)
35 {
36 printf("Board: Hitachi Power Grids %s\n", KM_BOARD_NAME);
37
38 return 0;
39 }
40
41 #define RSTRQSR1_WDT_RR 0x00200000
42 #define RSTRQSR1_SW_RR 0x00100000
43
board_early_init_f(void)44 int board_early_init_f(void)
45 {
46 struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
47 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
48 bool cpuwd_flag = false;
49
50 /* board specific IFC configuration: increased bus turnaround time */
51 setbits_be32(&ifc.gregs->ifc_gcr, 8 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
52
53 /* configure mode for uP reset request */
54 qrio_uprstreq(UPREQ_CORE_RST);
55
56 /* board only uses the DDR_MCK0, so disable the DDR_MCK1 */
57 setbits_be32(&gur->ddrclkdr, 0x40000000);
58
59 /* set reset reason according CPU register */
60 if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
61 RSTRQSR1_WDT_RR)
62 cpuwd_flag = true;
63
64 qrio_cpuwd_flag(cpuwd_flag);
65 /* clear CPU bits by writing 1 */
66 setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
67
68 /* configure PRST lines for the application: */
69 /*
70 * ETHSW_DDR_RST:
71 * reset at power-up and unit reset only and enable WD on it
72 */
73 qrio_prstcfg(KM_ETHSW_DDR_RST, PRSTCFG_POWUP_UNIT_RST);
74 qrio_wdmask(KM_ETHSW_DDR_RST, true);
75 /*
76 * XES_PHY_RST:
77 * reset at power-up and unit reset only and enable WD on it
78 */
79 qrio_prstcfg(KM_XES_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
80 qrio_wdmask(KM_XES_PHY_RST, true);
81 /*
82 * ES_PHY_RST:
83 * reset at power-up and unit reset only and enable WD on it
84 */
85 qrio_prstcfg(KM_ES_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
86 qrio_wdmask(KM_ES_PHY_RST, true);
87 /*
88 * EFE_RST:
89 * reset at power-up and unit reset only and enable WD on it
90 */
91 qrio_prstcfg(KM_EFE_RST, PRSTCFG_POWUP_UNIT_RST);
92 qrio_wdmask(KM_EFE_RST, true);
93 /*
94 * BFTIC4_RST:
95 * reset at power-up and unit reset only and enable WD on it
96 */
97 qrio_prstcfg(KM_BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
98 qrio_wdmask(KM_BFTIC4_RST, true);
99 /*
100 * DPAXE_RST:
101 * reset at power-up and unit reset only and enable WD on it
102 */
103 qrio_prstcfg(KM_DPAXE_RST, PRSTCFG_POWUP_UNIT_RST);
104 qrio_wdmask(KM_DPAXE_RST, true);
105 /*
106 * PEXSW_RST:
107 * reset at power-up and unit reset only, deassert reset w/o WD
108 */
109 qrio_prstcfg(KM_PEXSW_RST, PRSTCFG_POWUP_UNIT_RST);
110 qrio_prst(KM_PEXSW_RST, false, false);
111 /*
112 * PEXSW_NT_RST:
113 * reset at power-up and unit reset only, deassert reset w/o WD
114 */
115 qrio_prstcfg(KM_PEXSW_NT_RST, PRSTCFG_POWUP_UNIT_RST);
116 qrio_prst(KM_PEXSW_NT_RST, false, false);
117 /*
118 * BOBCAT_RST:
119 * reset at power-up and unit reset only, deassert reset w/o WD
120 */
121 qrio_prstcfg(KM_BOBCAT_RST, PRSTCFG_POWUP_UNIT_RST);
122 qrio_prst(KM_BOBCAT_RST, false, false);
123 /*
124 * FEMT_RST:
125 * reset at power-up and unit reset only and enable WD
126 */
127 qrio_prstcfg(KM_FEMT_RST, PRSTCFG_POWUP_UNIT_RST);
128 qrio_wdmask(KM_FEMT_RST, true);
129 /*
130 * FOAM_RST:
131 * reset at power-up and unit reset only and enable WD
132 */
133 qrio_prstcfg(KM_FOAM_RST, PRSTCFG_POWUP_UNIT_RST);
134 qrio_wdmask(KM_FOAM_RST, true);
135
136 return 0;
137 }
138
board_early_init_r(void)139 int board_early_init_r(void)
140 {
141 int ret = 0;
142
143 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
144 int flash_esel = find_tlb_idx((void *)flashbase, 1);
145
146 /*
147 * Remap Boot flash region to caching-inhibited
148 * so that flash can be erased properly.
149 */
150
151 /* Flush d-cache and invalidate i-cache of any FLASH data */
152 flush_dcache();
153 invalidate_icache();
154
155 if (flash_esel == -1) {
156 /* very unlikely unless something is messed up */
157 puts("Error: Could not find TLB for FLASH BASE\n");
158 flash_esel = 2; /* give our best effort to continue */
159 } else {
160 /* invalidate existing TLB entry for flash */
161 disable_tlb(flash_esel);
162 }
163
164 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
165 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
166 0, flash_esel, BOOKE_PAGESZ_256M, 1);
167
168 set_liodns();
169 setup_qbman_portals();
170
171 qrio_set_leds();
172
173 /* enable Application Buffer */
174 qrio_enable_app_buffer();
175
176 return ret;
177 }
178
get_serial_clock(unsigned long dummy)179 unsigned long get_serial_clock(unsigned long dummy)
180 {
181 return (gd->bus_clk / 2);
182 }
183
get_board_sys_clk(unsigned long dummy)184 unsigned long get_board_sys_clk(unsigned long dummy)
185 {
186 return 66666666;
187 }
188
misc_init_f(void)189 int misc_init_f(void)
190 {
191 /* configure QRIO pis for i2c deblocking */
192 i2c_deblock_gpio_cfg();
193
194 /*
195 * CFE_RST (front phy):
196 * reset at power-up, unit and core reset, deasset reset w/o WD
197 */
198 qrio_prstcfg(KM_CFE_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
199 qrio_prst(KM_CFE_RST, false, false);
200
201 /*
202 * ZL30158_RST (PTP clock generator):
203 * reset at power-up only, deassert reset and enable WD on it
204 */
205 qrio_prstcfg(KM_ZL30158_RST, PRSTCFG_POWUP_RST);
206 qrio_prst(KM_ZL30158_RST, false, false);
207
208 /*
209 * ZL30364_RST (EEC generator):
210 * reset at power-up only, deassert reset and enable WD on it
211 */
212 qrio_prstcfg(KM_ZL30364_RST, PRSTCFG_POWUP_RST);
213 qrio_prst(KM_ZL30364_RST, false, false);
214
215 return 0;
216 }
217
218 #define USED_SRDS_BANK 0
219 #define EXPECTED_SRDS_RFCK SRDS_PLLCR0_RFCK_SEL_100
220
221 #define BRG01_IOCLK12 0x02000000
222 #define EC2_GTX_CLK125 0x08000000
223
misc_init_r(void)224 int misc_init_r(void)
225 {
226 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
227 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_MPC85xx_SCFG;
228 ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
229
230 /* check SERDES bank 0 reference clock */
231 u32 actual = in_be32(®s->bank[USED_SRDS_BANK].pllcr0);
232
233 if (actual & SRDS_PLLCR0_POFF)
234 printf("Warning: SERDES bank %u pll is off\n", USED_SRDS_BANK);
235 if ((actual & SRDS_PLLCR0_RFCK_SEL_MASK) != EXPECTED_SRDS_RFCK) {
236 printf("Warning: SERDES bank %u expects %sMHz clock, is %sMHz\n",
237 USED_SRDS_BANK,
238 serdes_clock_to_string(EXPECTED_SRDS_RFCK),
239 serdes_clock_to_string(actual));
240 }
241
242 /* QE IO clk : BRG01 is used over clk12 for HDLC clk (20 MhZ) */
243 out_be32(&scfg->qeioclkcr,
244 in_be32(&scfg->qeioclkcr) | BRG01_IOCLK12);
245
246 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
247 CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
248
249 /* Fix polarity of Card Detect and Write Protect */
250 out_be32(&gur->sdhcpcr, 0xFFFFFFFF);
251
252 /*
253 * EC1 is disabled in our design, so we must explicitly set GTXCLKSEL
254 * to EC2
255 */
256 out_be32(&scfg->emiiocr, in_be32(&scfg->emiiocr) | EC2_GTX_CLK125);
257
258 return 0;
259 }
260
hush_init_var(void)261 int hush_init_var(void)
262 {
263 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
264 return 0;
265 }
266
last_stage_init(void)267 int last_stage_init(void)
268 {
269 const char *kmem;
270 /* DIP switch support on BFTIC */
271 struct bfticu_iomap *bftic4 =
272 (struct bfticu_iomap *)SYS_BFTIC_BASE;
273 u8 dip_switch = in_8((u8 *)&bftic4->mswitch) & BFTICU_DIPSWITCH_MASK;
274
275 if (dip_switch != 0) {
276 /* start bootloader */
277 puts("DIP: Enabled\n");
278 env_set("actual_bank", "0");
279 }
280
281 set_km_env();
282
283 /*
284 * bootm_size is used to fixup the FDT memory node
285 * set it to kernelmem that has the same value
286 */
287 kmem = env_get("kernelmem");
288 if (kmem)
289 env_set("bootm_size", kmem);
290
291 return 0;
292 }
293
fdt_fixup_fman_mac_addresses(void * blob)294 void fdt_fixup_fman_mac_addresses(void *blob)
295 {
296 int node, ret;
297 char path[24];
298 unsigned char mac_addr[6];
299
300 /*
301 * Just the fm1-mac5 must be set by us, u-boot handle the 2 others,
302 * get the mac addr from env
303 */
304 if (!eth_env_get_enetaddr_by_index("eth", 4, mac_addr)) {
305 printf("eth4addr env variable not defined\n");
306 return;
307 }
308
309 /* local management port */
310 strcpy(path, "/soc/fman/ethernet@e8000");
311 node = fdt_path_offset(blob, path);
312 if (node < 0) {
313 printf("no %s\n", path);
314 return;
315 }
316
317 ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
318 if (ret) {
319 printf("%s\n\terror setting local-mac-address property\n",
320 path);
321 }
322 }
323
ft_board_setup(void * blob,struct bd_info * bd)324 int ft_board_setup(void *blob, struct bd_info *bd)
325 {
326 phys_addr_t base;
327 phys_size_t size;
328
329 ft_cpu_setup(blob, bd);
330
331 base = env_get_bootm_low();
332 size = env_get_bootm_size();
333
334 fdt_fixup_memory(blob, (u64)base, (u64)size);
335
336 fdt_fixup_liodn(blob);
337
338 fdt_fixup_fman_mac_addresses(blob);
339
340 if (hwconfig("qe-tdm"))
341 fdt_del_diu(blob);
342 return 0;
343 }
344
345 /* DIC26_SELFTEST GPIO used to start factory test sw */
346 #define SELFTEST_PORT QRIO_GPIO_A
347 #define SELFTEST_PIN 0
348
post_hotkeys_pressed(void)349 int post_hotkeys_pressed(void)
350 {
351 qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
352 return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
353 }
354