1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2016 Keymile AG 4 * Rainer Boschung <rainer.boschung@keymile.com> 5 * 6 * Copyright 2013 Freescale Semiconductor, Inc. 7 */ 8 9 #include <asm/mmu.h> 10 #include <asm/u-boot.h> 11 12 struct fsl_e_tlb_entry tlb_table[] = { 13 /* TLB 0 - for temp stack in cache */ 14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 15 CONFIG_SYS_INIT_RAM_ADDR_PHYS, 16 MAS3_SX | MAS3_SW | MAS3_SR, 0, 17 0, 0, BOOKE_PAGESZ_4K, 0), 18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 19 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 20 MAS3_SX | MAS3_SW | MAS3_SR, 0, 21 0, 0, BOOKE_PAGESZ_4K, 0), 22 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 23 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 24 MAS3_SX | MAS3_SW | MAS3_SR, 0, 25 0, 0, BOOKE_PAGESZ_4K, 0), 26 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 27 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 28 MAS3_SX | MAS3_SW | MAS3_SR, 0, 29 0, 0, BOOKE_PAGESZ_4K, 0), 30 31 /* TLB 1 */ 32 /* *I*** - Covers boot page */ 33 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 34 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 35 0, 0, BOOKE_PAGESZ_4K, 1), 36 37 /* *I*G* - CCSRBAR */ 38 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 39 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 40 0, 1, BOOKE_PAGESZ_16M, 1), 41 42 /* *I*G* - Flash, localbus */ 43 /* This will be changed to *I*G* after relocation to RAM. */ 44 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 45 MAS3_SX | MAS3_SR, MAS2_W | MAS2_G, 46 0, 2, BOOKE_PAGESZ_128M, 1), 47 48 /* *I*G* - PCI1 */ 49 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 50 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 51 0, 3, BOOKE_PAGESZ_1G, 1), 52 53 /* *I*G* - PCI1 I/O */ 54 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 55 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 56 0, 4, BOOKE_PAGESZ_256K, 1), 57 58 /* Bman/Qman */ 59 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 60 MAS3_SX | MAS3_SW | MAS3_SR, 0, 61 0, 5, BOOKE_PAGESZ_16M, 1), 62 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, 63 CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, 64 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 65 0, 6, BOOKE_PAGESZ_16M, 1), 66 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 67 MAS3_SX | MAS3_SW | MAS3_SR, 0, 68 0, 7, BOOKE_PAGESZ_16M, 1), 69 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, 70 CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, 71 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 72 0, 8, BOOKE_PAGESZ_16M, 1), 73 74 SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 75 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 76 0, 9, BOOKE_PAGESZ_4M, 1), 77 78 /* *I*G - NAND */ 79 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 80 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 81 0, 10, BOOKE_PAGESZ_64K, 1), 82 /* QRIO */ 83 SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS, 84 MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 85 0, 11, BOOKE_PAGESZ_64K, 1), 86 /* MRAM */ 87 SET_TLB_ENTRY(1, CONFIG_SYS_MRAM_BASE, SYS_MRAM_BASE_PHYS, 88 MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 89 0, 12, BOOKE_PAGESZ_128M, 1), 90 /* BFTIC */ 91 SET_TLB_ENTRY(1, SYS_BFTIC_BASE, SYS_BFTIC_BASE_PHYS, 92 MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 93 0, 13, BOOKE_PAGESZ_128M, 1), 94 /* 95 * entry 14 and 15 has been used hard coded, they will be disabled 96 * in cpu_init_f, so do not use them here!!. 97 */ 98 /* PAXE */ 99 SET_TLB_ENTRY(1, CONFIG_SYS_PAXE_BASE, SYS_PAXE_BASE_PHYS, 100 MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 101 0, 16, BOOKE_PAGESZ_128M, 1) 102 }; 103 104 int num_tlb_entries = ARRAY_SIZE(tlb_table); 105