1 // SPDX-License-Identifier: GPL-2.0+
2
3 #include <common.h>
4 #include <malloc.h>
5 #include <errno.h>
6 #include <fsl_ddr.h>
7 #include <fdt_support.h>
8 #include <asm/global_data.h>
9 #include <linux/libfdt.h>
10 #include <env_internal.h>
11 #include <asm/arch-fsl-layerscape/soc.h>
12 #include <asm/arch-fsl-layerscape/fsl_icid.h>
13 #include <i2c.h>
14 #include <asm/arch/soc.h>
15 #include <fsl_immap.h>
16 #include <netdev.h>
17
18 #include <fdtdec.h>
19 #include <miiphy.h>
20
21 DECLARE_GLOBAL_DATA_PTR;
22
board_early_init_f(void)23 int board_early_init_f(void)
24 {
25 fsl_lsch3_early_init_f();
26 return 0;
27 }
28
board_init(void)29 int board_init(void)
30 {
31 if (CONFIG_IS_ENABLED(FSL_CAAM))
32 sec_init();
33
34 return 0;
35 }
36
board_eth_init(struct bd_info * bis)37 int board_eth_init(struct bd_info *bis)
38 {
39 return pci_eth_init(bis);
40 }
41
checkboard(void)42 int checkboard(void)
43 {
44 printf("EL: %d\n", current_el());
45 return 0;
46 }
47
detail_board_ddr_info(void)48 void detail_board_ddr_info(void)
49 {
50 puts("\nDDR ");
51 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
52 print_ddr_info(0);
53 }
54
ft_board_setup(void * blob,struct bd_info * bd)55 int ft_board_setup(void *blob, struct bd_info *bd)
56 {
57 u64 base[CONFIG_NR_DRAM_BANKS];
58 u64 size[CONFIG_NR_DRAM_BANKS];
59 int nbanks = CONFIG_NR_DRAM_BANKS;
60 int node;
61 int i;
62
63 ft_cpu_setup(blob, bd);
64
65 /* fixup DT for the two GPP DDR banks */
66 for (i = 0; i < nbanks; i++) {
67 base[i] = gd->bd->bi_dram[i].start;
68 size[i] = gd->bd->bi_dram[i].size;
69 }
70
71 fdt_fixup_memory_banks(blob, base, size, nbanks);
72
73 fdt_fixup_icid(blob);
74
75 if (CONFIG_IS_ENABLED(SL28_SPL_LOADS_OPTEE_BL32)) {
76 node = fdt_node_offset_by_compatible(blob, -1, "linaro,optee-tz");
77 if (node)
78 fdt_set_node_status(blob, node, FDT_STATUS_OKAY, 0);
79 }
80
81 return 0;
82 }
83