1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 */
4
5 #include <common.h>
6 #include <init.h>
7 #include <asm/global_data.h>
8 #include <asm/io.h>
9 #include <asm/arch/at91sam9x5_matrix.h>
10 #include <asm/arch/at91sam9_smc.h>
11 #include <asm/arch/at91_common.h>
12 #include <asm/arch/at91_rstc.h>
13 #include <asm/arch/clk.h>
14 #include <asm/arch/gpio.h>
15 #include <net.h>
16 #include <netdev.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 /* ------------------------------------------------------------------------- */
21 /*
22 * Miscelaneous platform dependent initialisations
23 */
wb45n_nand_hw_init(void)24 static void wb45n_nand_hw_init(void)
25 {
26 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
27 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
28 unsigned long csa;
29
30 csa = readl(&matrix->ebicsa);
31 /* Enable CS3 */
32 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
33 /* NAND flash on D0 */
34 csa &= ~AT91_MATRIX_NFD0_ON_D16;
35 writel(csa, &matrix->ebicsa);
36
37 /* Configure SMC CS3 for NAND/SmartMedia */
38 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
39 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
40 &smc->cs[3].setup);
41 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
42 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
43 &smc->cs[3].pulse);
44 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
45 &smc->cs[3].cycle);
46 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
47 AT91_SMC_MODE_EXNW_DISABLE |
48 AT91_SMC_MODE_DBW_8 |
49 AT91_SMC_MODE_TDF_CYCLE(1), &smc->cs[3].mode);
50
51 at91_periph_clk_enable(ATMEL_ID_PIOCD);
52
53 /* Configure RDY/BSY */
54 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
55 /* Enable NandFlash */
56 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
57 /* Disable Flash Write Protect Line */
58 at91_set_gpio_output(AT91_PIN_PD10, 1);
59
60 at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
61 at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
62 at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
63 at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
64 }
65
wb45n_gpio_hw_init(void)66 static void wb45n_gpio_hw_init(void)
67 {
68
69 /* Configure wifi gpio CHIP_PWD_L */
70 at91_set_gpio_output(AT91_PIN_PA28, 0);
71
72 /* Setup USB pins */
73 at91_set_gpio_input(AT91_PIN_PB11, 0);
74 at91_set_gpio_output(AT91_PIN_PB12, 0);
75
76 /* IRQ pin, pullup, deglitch */
77 at91_set_gpio_input(AT91_PIN_PB18, 1);
78 at91_set_gpio_deglitch(AT91_PIN_PB18, 1);
79 }
80
board_eth_init(struct bd_info * bis)81 int board_eth_init(struct bd_info *bis)
82 {
83 int rc = 0;
84
85 if (has_emac0())
86 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
87
88 return rc;
89 }
90
board_early_init_f(void)91 int board_early_init_f(void)
92 {
93 at91_seriald_hw_init();
94 return 0;
95 }
96
board_init(void)97 int board_init(void)
98 {
99 /* address of boot parameters */
100 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
101
102 wb45n_gpio_hw_init();
103
104 wb45n_nand_hw_init();
105
106 at91_macb_hw_init();
107
108 return 0;
109 }
110
dram_init(void)111 int dram_init(void)
112 {
113 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
114 CONFIG_SYS_SDRAM_SIZE);
115 return 0;
116 }
117
118 #if defined(CONFIG_SPL_BUILD)
119 #include <spl.h>
120 #include <nand.h>
121
at91_spl_board_init(void)122 void at91_spl_board_init(void)
123 {
124 /* Setup GPIO first */
125 wb45n_gpio_hw_init();
126
127 /* Bring up NAND */
128 wb45n_nand_hw_init();
129 }
130
matrix_init(void)131 void matrix_init(void)
132 {
133 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
134 unsigned long csa;
135
136 csa = readl(&matrix->ebicsa);
137 /* Pull ups on D0 - D16 */
138 csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
139 csa |= AT91_MATRIX_EBI_DBPD_OFF;
140 /* Normal drive strength */
141 csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
142 /* Multi-port off */
143 csa &= ~AT91_MATRIX_MP_ON;
144 writel(csa, &matrix->ebicsa);
145 }
146
147 #include <asm/arch/atmel_mpddrc.h>
ddr2_conf(struct atmel_mpddrc_config * ddr2)148 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
149 {
150 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM);
151
152 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
153 ATMEL_MPDDRC_CR_NR_ROW_13 |
154 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
155 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
156 ATMEL_MPDDRC_CR_DQMS_SHARED);
157
158 ddr2->rtr = 0x411;
159
160 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
161 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
162 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
163 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
164 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
165 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
166 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
167 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
168
169 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
170 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
171 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
172 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
173
174 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
175 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
176 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
177 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
178 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
179 }
180
mem_init(void)181 void mem_init(void)
182 {
183 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
184 struct atmel_mpddrc_config ddr2;
185 unsigned long csa;
186
187 ddr2_conf(&ddr2);
188
189 /* enable DDR2 clock */
190 at91_system_clk_enable(AT91_PMC_DDR);
191
192 /* Chip select 1 is for DDR2/SDRAM */
193 csa = readl(&matrix->ebicsa);
194 csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
195 writel(csa, &matrix->ebicsa);
196
197 /* DDRAM2 Controller initialize */
198 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
199 }
200 #endif
201