1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * DENX M28 Boot setup
4 *
5 * Copyright (C) 2019 DENX Software Engineering
6 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
7 *
8 * Copyright (C) 2018 DENX Software Engineering
9 * Måns Rullgård, DENX Software Engineering, mans@mansr.com
10 *
11 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
12 * on behalf of DENX Software Engineering GmbH
13 */
14
15 #include <common.h>
16 #include <config.h>
17 #include <asm/io.h>
18 #include <asm/arch/iomux-mx28.h>
19 #include <asm/arch/imx-regs.h>
20 #include <asm/arch/sys_proto.h>
21
22 #define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
23 #define MUX_CONFIG_BOOT (MXS_PAD_3V3)
24 #define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
25 #define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
26 #define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
27 #define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL)
28 #define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
29
30 const iomux_cfg_t iomux_setup[] = {
31 /* AUART0 IRDA */
32 MX28_PAD_AUART0_RX__AUART0_RX,
33 MX28_PAD_AUART0_TX__AUART0_TX,
34
35 /* AUART 4 RS422 */
36 MX28_PAD_AUART0_CTS__AUART4_RX,
37 MX28_PAD_AUART0_RTS__AUART4_TX,
38
39 /* USB0 */
40 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT,
41 MX28_PAD_AUART1_RTS__USB0_ID,
42 MX28_PAD_LCD_VSYNC__GPIO_1_28, /* PRW_On */
43
44 /* USB1 */
45 MX28_PAD_PWM2__USB1_OVERCURRENT,
46
47 /* eMMC */
48 MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
49 MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
50 MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
51 MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
52 MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
53 MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
54 MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
55 MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
56 MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
57 MX28_PAD_SSP0_DETECT__GPIO_2_9, /* Reset for eMMC */
58 MX28_PAD_SSP0_SCK__SSP0_SCK | MUX_CONFIG_SSP0,
59
60 /* DIG Keys */
61 MX28_PAD_GPMI_D00__GPIO_0_0,
62 MX28_PAD_GPMI_D01__GPIO_0_1,
63 MX28_PAD_GPMI_D02__GPIO_0_2,
64 MX28_PAD_GPMI_D03__GPIO_0_3,
65 MX28_PAD_GPMI_D04__GPIO_0_4,
66 MX28_PAD_GPMI_D05__GPIO_0_5,
67 MX28_PAD_GPMI_D06__GPIO_0_6,
68 MX28_PAD_GPMI_D07__GPIO_0_7,
69
70 /* ADR_0-2 */
71 MX28_PAD_GPMI_CE1N__GPIO_0_17,
72 MX28_PAD_GPMI_CE2N__GPIO_0_18,
73 MX28_PAD_GPMI_CE3N__GPIO_0_19,
74
75 /* Read Keys */
76 MX28_PAD_GPMI_RDY0__GPIO_0_20,
77
78 /* LATCH_EN */
79 MX28_PAD_GPMI_RDY1__GPIO_0_21,
80
81 /* Power off */
82 MX28_PAD_GPMI_RDN__GPIO_0_24,
83
84 /* I2C1 Touch */
85 MX28_PAD_AUART2_CTS__GPIO_3_10,
86 MX28_PAD_AUART2_RTS__GPIO_3_11,
87 MX28_PAD_GPMI_RDY2__GPIO_0_22, /* Touch Reset */
88
89 /* TIVA */
90 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT,
91 MX28_PAD_SSP2_MISO__SSP2_D0,
92 MX28_PAD_SSP2_MOSI__SSP2_CMD,
93 MX28_PAD_SSP2_SCK__SSP2_SCK,
94 MX28_PAD_SSP2_SS0__SSP2_D3,
95 MX28_PAD_SSP2_SS1__GPIO_2_20,
96 MX28_PAD_SSP2_SS2__GPIO_2_21,
97
98 /* SPI3 NOR-Flash */
99 MX28_PAD_AUART1_TX__SSP3_CARD_DETECT,
100 MX28_PAD_AUART2_RX__SSP3_D1,
101 MX28_PAD_AUART2_TX__SSP3_D2,
102 MX28_PAD_SSP3_MISO__SSP3_D0,
103 MX28_PAD_SSP3_MOSI__SSP3_CMD,
104 MX28_PAD_SSP3_SCK__SSP3_SCK,
105 MX28_PAD_SSP3_SS0__SSP3_D3,
106
107 /* NOR-Flash CMD */
108 MX28_PAD_LCD_RS__GPIO_1_26, /* Hold */
109 MX28_PAD_LCD_WR_RWN__GPIO_1_25, /* write protect */
110
111 /* I2C0 Codec */
112 MX28_PAD_I2C0_SCL__I2C0_SCL,
113 MX28_PAD_I2C0_SDA__I2C0_SDA,
114
115 /* I2S Codec */
116 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK,
117 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK,
118 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK,
119 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0,
120 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0,
121
122 /* PWR-Hold */
123 MX28_PAD_SPDIF__GPIO_3_27,
124
125 /* EMI */
126 MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
127 MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
128 MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
129 MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
130 MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
131 MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
132 MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
133 MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
134 MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
135 MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
136 MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
137 MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
138 MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
139 MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
140 MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
141 MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
142 MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
143 MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
144 MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
145 MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
146 MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
147 MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
148 MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
149 MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
150 MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
151
152 MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
153 MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
154 MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
155 MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
156 MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
157 MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
158 MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
159 MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
160 MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
161 MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
162 MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
163 MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
164 MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
165 MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
166 MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
167 MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
168 MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
169 MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
170 MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
171 MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
172 MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
173 MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
174 MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
175 MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
176
177 /* Uart3 Bluetooth-Interface */
178 MX28_PAD_AUART3_CTS__AUART3_CTS,
179 MX28_PAD_AUART3_RTS__AUART3_RTS,
180 MX28_PAD_AUART3_RX__AUART3_RX,
181 MX28_PAD_AUART3_TX__AUART3_TX,
182
183 /* framebuffer */
184 MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
185 MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
186 MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
187 MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
188 MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
189 MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
190 MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
191 MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
192 MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
193 MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
194 MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
195 MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
196 MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
197 MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
198 MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
199 MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
200 MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
201 MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
202 MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
203 MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
204 MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
205 MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
206 MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
207 MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
208 MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
209 MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD,
210 MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
211 MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD,
212 MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD,
213 MX28_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD,
214
215 /* DUART RS232 */
216 MX28_PAD_PWM0__DUART_RX,
217 MX28_PAD_PWM1__DUART_TX,
218
219 /* FEC Ethernet */
220 MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
221 MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
222 MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
223 MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
224 MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
225 MX28_PAD_ENET0_RX_CLK__GPIO_4_13, /* Phy Interrupt */
226 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
227 MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
228 MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
229 MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
230 MX28_PAD_ENET0_TX_CLK__GPIO_4_5, /* n.c. */
231 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
232 MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
233 MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
234 MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
235 MX28_PAD_SSP1_CMD__GPIO_2_13, /* PHY reset */
236
237 /* TIVA boot control */
238 MX28_PAD_GPMI_RDY3__GPIO_0_23 | MUX_CONFIG_BOOT, /* TIVA0 */
239 MX28_PAD_GPMI_WRN__GPIO_0_25 | MUX_CONFIG_BOOT, /* TIVA1 */
240 };
241
242 u32 mxs_dram_vals[] = {
243 0x00000000, 0x00000000, 0x00000000, 0x00000000,
244 0x00000000, 0x00000000, 0x00000000, 0x00000000,
245 0x00000000, 0x00000000, 0x00000000, 0x00000000,
246 0x00000000, 0x00000000, 0x00000000, 0x00000000,
247 0x00000000, 0x00000100, 0x00000000, 0x00000000,
248 0x00000000, 0x00000000, 0x00000000, 0x00000000,
249 0x00000000, 0x00000000, 0x00010101, 0x01010101,
250 0x000f0f01, 0x0f02010a, 0x00000000, 0x00010101,
251 0x00000100, 0x00000100, 0x00000000, 0x00000002,
252 0x01010000, 0x07080403, 0x07005303, 0x0b0000c8,
253 0x0200a0c1, 0x0002040c, 0x0038430a, 0x04290322,
254 0x02040203, 0x00c8002b, 0x00000000, 0x00000000,
255 0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
256 0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
257 0x00000003, 0x00000000, 0x00000000, 0x00000000,
258 0x00000000, 0x00000000, 0x00000000, 0x00000000,
259 0x00000000, 0x00000000, 0x00000612, 0x01000102,
260 0x06120612, 0x00000200, 0x00020007, 0xf4004a27,
261 0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07400300,
262 0x07400300, 0x07400300, 0x07400300, 0x00000005,
263 0x00000000, 0x00000000, 0x01000000, 0x00000000,
264 0x00000001, 0x000f1133, 0x00000000, 0x00001f04,
265 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
266 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000,
267 0x00000000, 0x00000000, 0x00000000, 0x00000000,
268 0x00000000, 0x00000000, 0x00000000, 0x00000000,
269 0x00000000, 0x00000000, 0x00000000, 0x00000000,
270 0x00000000, 0x00000000, 0x00000000, 0x00000000,
271 0x00000000, 0x00000000, 0x00000000, 0x00000000,
272 0x00000000, 0x00000000, 0x00000000, 0x00000000,
273 0x00000000, 0x00000000, 0x00000000, 0x00000000,
274 0x00000000, 0x00000000, 0x00000000, 0x00000000,
275 0x00000000, 0x00000000, 0x00000000, 0x00000000,
276 0x00000000, 0x00000000, 0x00000000, 0x00000000,
277 0x00000000, 0x00000000, 0x00000000, 0x00000000,
278 0x00000000, 0x00000000, 0x00000000, 0x00000000,
279 0x00000000, 0x00000000, 0x00000000, 0x00000000,
280 0x00000000, 0x00000000, 0x00000000, 0x00000000,
281 0x00000000, 0x00000000, 0x00000000, 0x00000000,
282 0x00000000, 0x00000000, 0x00000000, 0x00000000,
283 0x00000000, 0x00000000, 0x00010000, 0x00030404,
284 0x00000002, 0x00000000, 0x00000000, 0x00000000,
285 0x00000000, 0x00000000, 0x00000000, 0x01010000,
286 0x01000000, 0x03030000, 0x00010303, 0x01020202,
287 0x00000000, 0x02040101, 0x21002103, 0x00061200,
288 0x06120612, 0x00000642, 0x00000000, 0x00000004,
289 0x00000000, 0x00000080, 0x00000000, 0x00000000,
290 0x00000000, 0xffffffff
291 };
292
lowlevel_init(void)293 void lowlevel_init(void)
294 {
295 struct mxs_pinctrl_regs *pinctrl_regs =
296 (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
297
298 /* Set EMI drive strength */
299 writel(0x00003fff, &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_clr);
300 writel(0x00002aaa, &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
301
302 mxs_common_spl_init(0, NULL, iomux_setup, ARRAY_SIZE(iomux_setup));
303 }
304