1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Stefano Babic <sbabic@denx.de>
4 */
5
6 #include <common.h>
7 #include <cpu_func.h>
8 #include <init.h>
9 #include <log.h>
10 #include <net.h>
11 #include <asm/global_data.h>
12 #include <asm/io.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/iomux.h>
16 #include <asm/arch/crm_regs.h>
17 #include <asm/arch/iomux.h>
18 #include <asm/arch/mx6-pins.h>
19 #include <asm/mach-imx/iomux-v3.h>
20 #include <asm/mach-imx/boot_mode.h>
21 #include <asm/mach-imx/mxc_i2c.h>
22 #include <asm/mach-imx/spi.h>
23 #include <env.h>
24 #include <linux/delay.h>
25 #include <linux/errno.h>
26 #include <asm/gpio.h>
27 #include <mmc.h>
28 #include <i2c.h>
29 #include <fsl_esdhc_imx.h>
30 #include <nand.h>
31 #include <miiphy.h>
32 #include <netdev.h>
33 #include <asm/arch/sys_proto.h>
34 #include <asm/sections.h>
35
36 DECLARE_GLOBAL_DATA_PTR;
37
38 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
39 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
40 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
41
42 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
43 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
44 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
45
46 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
47 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
48
49 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
50 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
51
52 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
53 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
54 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
55
56 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
57
58 #define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
59 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
60
61 #define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
62 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
63
64 #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14)
65 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
66 #define GREEN_LED IMX_GPIO_NR(2, 31)
67 #define RED_LED IMX_GPIO_NR(1, 30)
68 #define IMX6Q_DRIVE_STRENGTH 0x30
69
dram_init(void)70 int dram_init(void)
71 {
72 gd->ram_size = imx_ddr_size();
73 return 0;
74 }
75
76 static iomux_v3_cfg_t const uart4_pads[] = {
77 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
78 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
79 };
80
81 static iomux_v3_cfg_t const enet_pads[] = {
82 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
83 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
84 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
85 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
86 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
87 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
88 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
89 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
90 MUX_PAD_CTRL(ENET_PAD_CTRL)),
91 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
92 MUX_PAD_CTRL(ENET_PAD_CTRL)),
93 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
94 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
95 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
96 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
97 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
98 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
99 MUX_PAD_CTRL(ENET_PAD_CTRL)),
100 IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
101 };
102
103 static iomux_v3_cfg_t const ecspi3_pads[] = {
104 IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
105 IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
106 IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
107 IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
108 };
109
110 static iomux_v3_cfg_t const gpios_pads[] = {
111 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
112 IOMUX_PADS(PAD_SD4_DAT4__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
113 IOMUX_PADS(PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
114 IOMUX_PADS(PAD_SD4_DAT6__GPIO2_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
115 IOMUX_PADS(PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
116 IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
117 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
118 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
119 };
120
121 #if defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD)
122 /* NAND */
123 static iomux_v3_cfg_t const nfc_pads[] = {
124 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL)),
125 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL)),
126 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
127 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
128 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
129 IOMUX_PADS(PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
130 IOMUX_PADS(PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
131 IOMUX_PADS(PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
132 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
133 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL)),
134 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
135 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
136 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
137 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
138 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
139 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
140 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
141 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL)),
142 IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL)),
143 };
144 #endif
145
146 static struct i2c_pads_info i2c_pad_info = {
147 .scl = {
148 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | I2C_PAD,
149 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | I2C_PAD,
150 .gp = IMX_GPIO_NR(3, 21)
151 },
152 .sda = {
153 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | I2C_PAD,
154 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | I2C_PAD,
155 .gp = IMX_GPIO_NR(3, 28)
156 }
157 };
158
159 static struct fsl_esdhc_cfg usdhc_cfg[] = {
160 {USDHC3_BASE_ADDR,
161 .max_bus_width = 4},
162 {.esdhc_base = USDHC2_BASE_ADDR,
163 .max_bus_width = 4},
164 };
165
166 #if !defined(CONFIG_SPL_BUILD)
167 static iomux_v3_cfg_t const usdhc2_pads[] = {
168 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
169 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
170 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
171 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
172 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
173 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
174 IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
175 IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
176 };
177 #endif
178
179 static iomux_v3_cfg_t const usdhc3_pads[] = {
180 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
181 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
182 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
183 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
184 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
185 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
186 IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
187 IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
188 IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
189 IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
190 };
191
board_mmc_get_env_dev(int devno)192 int board_mmc_get_env_dev(int devno)
193 {
194 return devno - 1;
195 }
196
board_mmc_getcd(struct mmc * mmc)197 int board_mmc_getcd(struct mmc *mmc)
198 {
199 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
200 int ret = 0;
201
202 switch (cfg->esdhc_base) {
203 case USDHC2_BASE_ADDR:
204 ret = !gpio_get_value(USDHC2_CD_GPIO);
205 ret = 1;
206 break;
207 case USDHC3_BASE_ADDR:
208 ret = 1;
209 break;
210 }
211
212 return ret;
213 }
214
215 #ifndef CONFIG_SPL_BUILD
board_mmc_init(struct bd_info * bis)216 int board_mmc_init(struct bd_info *bis)
217 {
218 int ret;
219 int i;
220
221 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
222 switch (i) {
223 case 0:
224 SETUP_IOMUX_PADS(usdhc3_pads);
225 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
226 break;
227 case 1:
228 SETUP_IOMUX_PADS(usdhc2_pads);
229 gpio_direction_input(USDHC2_CD_GPIO);
230 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
231 break;
232 default:
233 printf("Warning: you configured more USDHC controllers"
234 "(%d) then supported by the board (%d)\n",
235 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
236 return -EINVAL;
237 }
238
239 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
240 if (ret)
241 return ret;
242 }
243
244 return 0;
245 }
246 #endif
247
setup_iomux_uart(void)248 static void setup_iomux_uart(void)
249 {
250 SETUP_IOMUX_PADS(uart4_pads);
251 }
252
setup_iomux_enet(void)253 static void setup_iomux_enet(void)
254 {
255 SETUP_IOMUX_PADS(enet_pads);
256
257 gpio_direction_output(ENET_PHY_RESET_GPIO, 0);
258 mdelay(10);
259 gpio_set_value(ENET_PHY_RESET_GPIO, 1);
260 mdelay(30);
261 }
262
setup_spi(void)263 static void setup_spi(void)
264 {
265 gpio_request(IMX_GPIO_NR(4, 24), "spi_cs0");
266 gpio_direction_output(IMX_GPIO_NR(4, 24), 1);
267
268 SETUP_IOMUX_PADS(ecspi3_pads);
269
270 enable_spi_clk(true, 2);
271 }
272
setup_gpios(void)273 static void setup_gpios(void)
274 {
275 SETUP_IOMUX_PADS(gpios_pads);
276 }
277
278 #if defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD)
setup_gpmi_nand(void)279 static void setup_gpmi_nand(void)
280 {
281 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
282
283 /* config gpmi nand iomux */
284 SETUP_IOMUX_PADS(nfc_pads);
285
286 /* gate ENFC_CLK_ROOT clock first,before clk source switch */
287 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
288
289 /* config gpmi and bch clock to 100 MHz */
290 clrsetbits_le32(&mxc_ccm->cs2cdr,
291 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
292 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
293 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
294 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
295 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
296 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
297
298 /* enable ENFC_CLK_ROOT clock */
299 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
300
301 /* enable gpmi and bch clock gating */
302 setbits_le32(&mxc_ccm->CCGR4,
303 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
304 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
305 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
306 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
307 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
308
309 /* enable apbh clock gating */
310 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
311 }
312 #endif
313
314 /*
315 * Board revision is coded in 4 GPIOs
316 */
get_board_rev(void)317 u32 get_board_rev(void)
318 {
319 u32 rev;
320 int i;
321
322 for (i = 0, rev = 0; i < 4; i++)
323 rev |= (gpio_get_value(IMX_GPIO_NR(2, 12 + i)) << i);
324
325 return 16 - rev;
326 }
327
board_spi_cs_gpio(unsigned bus,unsigned cs)328 int board_spi_cs_gpio(unsigned bus, unsigned cs)
329 {
330 if (bus != 2 || (cs != 0))
331 return -EINVAL;
332
333 return IMX_GPIO_NR(4, 24);
334 }
335
board_eth_init(struct bd_info * bis)336 int board_eth_init(struct bd_info *bis)
337 {
338 setup_iomux_enet();
339
340 return cpu_eth_init(bis);
341 }
342
board_early_init_f(void)343 int board_early_init_f(void)
344 {
345 setup_iomux_uart();
346
347 return 0;
348 }
349
board_init(void)350 int board_init(void)
351 {
352 /* address of boot parameters */
353 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
354
355 #ifdef CONFIG_SYS_I2C_MXC
356 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info);
357 #endif
358
359 #ifdef CONFIG_MXC_SPI
360 setup_spi();
361 #endif
362
363 setup_gpios();
364
365 #if defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD)
366 setup_gpmi_nand();
367 #endif
368 return 0;
369 }
370
371
372 #ifdef CONFIG_CMD_BMODE
373 /*
374 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
375 * see Table 8-11 and Table 5-9
376 * BOOT_CFG1[7] = 1 (boot from NAND)
377 * BOOT_CFG1[5] = 0 - raw NAND
378 * BOOT_CFG1[4] = 0 - default pad settings
379 * BOOT_CFG1[3:2] = 00 - devices = 1
380 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
381 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
382 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
383 * BOOT_CFG2[0] = 0 - Reset time 12ms
384 */
385 static const struct boot_mode board_boot_modes[] = {
386 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
387 {"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)},
388 {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
389 {NULL, 0},
390 };
391 #endif
392
board_late_init(void)393 int board_late_init(void)
394 {
395 char buf[10];
396 #ifdef CONFIG_CMD_BMODE
397 add_board_boot_modes(board_boot_modes);
398 #endif
399
400 snprintf(buf, sizeof(buf), "%d", get_board_rev());
401 env_set("board_rev", buf);
402
403 return 0;
404 }
405
406 #ifdef CONFIG_SPL_BUILD
407 #include <asm/arch/mx6-ddr.h>
408 #include <spl.h>
409 #include <linux/libfdt.h>
410
411 #define MX6_PHYFLEX_ERR006282 IMX_GPIO_NR(2, 11)
phyflex_err006282_workaround(void)412 static void phyflex_err006282_workaround(void)
413 {
414 /*
415 * Boards beginning with 1362.2 have the SD4_DAT3 pin connected
416 * to the CMIC. If this pin isn't toggled within 10s the boards
417 * reset. The pin is unconnected on older boards, so we do not
418 * need a check for older boards before applying this fixup.
419 */
420
421 gpio_direction_output(MX6_PHYFLEX_ERR006282, 0);
422 mdelay(2);
423 gpio_direction_output(MX6_PHYFLEX_ERR006282, 1);
424 mdelay(2);
425 gpio_set_value(MX6_PHYFLEX_ERR006282, 0);
426
427 gpio_direction_input(MX6_PHYFLEX_ERR006282);
428 }
429
430 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
431 .dram_sdclk_0 = 0x00000030,
432 .dram_sdclk_1 = 0x00000030,
433 .dram_cas = 0x00000030,
434 .dram_ras = 0x00000030,
435 .dram_reset = 0x00000030,
436 .dram_sdcke0 = 0x00003000,
437 .dram_sdcke1 = 0x00003000,
438 .dram_sdba2 = 0x00000030,
439 .dram_sdodt0 = 0x00000030,
440 .dram_sdodt1 = 0x00000030,
441
442 .dram_sdqs0 = 0x00000028,
443 .dram_sdqs1 = 0x00000028,
444 .dram_sdqs2 = 0x00000028,
445 .dram_sdqs3 = 0x00000028,
446 .dram_sdqs4 = 0x00000028,
447 .dram_sdqs5 = 0x00000028,
448 .dram_sdqs6 = 0x00000028,
449 .dram_sdqs7 = 0x00000028,
450 .dram_dqm0 = 0x00000028,
451 .dram_dqm1 = 0x00000028,
452 .dram_dqm2 = 0x00000028,
453 .dram_dqm3 = 0x00000028,
454 .dram_dqm4 = 0x00000028,
455 .dram_dqm5 = 0x00000028,
456 .dram_dqm6 = 0x00000028,
457 .dram_dqm7 = 0x00000028,
458 };
459
460 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
461 .grp_ddr_type = 0x000C0000,
462 .grp_ddrmode_ctl = 0x00020000,
463 .grp_ddrpke = 0x00000000,
464 .grp_addds = IMX6Q_DRIVE_STRENGTH,
465 .grp_ctlds = IMX6Q_DRIVE_STRENGTH,
466 .grp_ddrmode = 0x00020000,
467 .grp_b0ds = 0x00000028,
468 .grp_b1ds = 0x00000028,
469 .grp_b2ds = 0x00000028,
470 .grp_b3ds = 0x00000028,
471 .grp_b4ds = 0x00000028,
472 .grp_b5ds = 0x00000028,
473 .grp_b6ds = 0x00000028,
474 .grp_b7ds = 0x00000028,
475 };
476
477 static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
478 .p0_mpwldectrl0 = 0x00110011,
479 .p0_mpwldectrl1 = 0x00240024,
480 .p1_mpwldectrl0 = 0x00260038,
481 .p1_mpwldectrl1 = 0x002C0038,
482 .p0_mpdgctrl0 = 0x03400350,
483 .p0_mpdgctrl1 = 0x03440340,
484 .p1_mpdgctrl0 = 0x034C0354,
485 .p1_mpdgctrl1 = 0x035C033C,
486 .p0_mprddlctl = 0x322A2A2A,
487 .p1_mprddlctl = 0x302C2834,
488 .p0_mpwrdlctl = 0x34303834,
489 .p1_mpwrdlctl = 0x422A3E36,
490 };
491
492 /* Index in RAM Chip array */
493 enum {
494 RAM_MT64K,
495 RAM_MT128K,
496 RAM_MT256K
497 };
498
499 static struct mx6_ddr3_cfg mt41k_xx[] = {
500 /* MT41K64M16JT-125 (1Gb density) */
501 {
502 .mem_speed = 1600,
503 .density = 1,
504 .width = 16,
505 .banks = 8,
506 .rowaddr = 13,
507 .coladdr = 10,
508 .pagesz = 2,
509 .trcd = 1375,
510 .trcmin = 4875,
511 .trasmin = 3500,
512 .SRT = 1,
513 },
514
515 /* MT41K256M16JT-125 (2Gb density) */
516 {
517 .mem_speed = 1600,
518 .density = 2,
519 .width = 16,
520 .banks = 8,
521 .rowaddr = 14,
522 .coladdr = 10,
523 .pagesz = 2,
524 .trcd = 1375,
525 .trcmin = 4875,
526 .trasmin = 3500,
527 .SRT = 1,
528 },
529
530 /* MT41K256M16JT-125 (4Gb density) */
531 {
532 .mem_speed = 1600,
533 .density = 4,
534 .width = 16,
535 .banks = 8,
536 .rowaddr = 15,
537 .coladdr = 10,
538 .pagesz = 2,
539 .trcd = 1375,
540 .trcmin = 4875,
541 .trasmin = 3500,
542 .SRT = 1,
543 }
544 };
545
ccgr_init(void)546 static void ccgr_init(void)
547 {
548 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
549
550 writel(0x00C03F3F, &ccm->CCGR0);
551 writel(0x0030FC03, &ccm->CCGR1);
552 writel(0x0FFFC000, &ccm->CCGR2);
553 writel(0x3FF00000, &ccm->CCGR3);
554 writel(0x00FFF300, &ccm->CCGR4);
555 writel(0x0F0000C3, &ccm->CCGR5);
556 writel(0x000003FF, &ccm->CCGR6);
557 }
558
spl_dram_init(struct mx6_ddr_sysinfo * sysinfo,struct mx6_ddr3_cfg * mem_ddr)559 static void spl_dram_init(struct mx6_ddr_sysinfo *sysinfo,
560 struct mx6_ddr3_cfg *mem_ddr)
561 {
562 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
563 mx6_dram_cfg(sysinfo, &mx6_mmcd_calib, mem_ddr);
564 }
565
board_mmc_init(struct bd_info * bis)566 int board_mmc_init(struct bd_info *bis)
567 {
568 if (spl_boot_device() == BOOT_DEVICE_SPI)
569 printf("MMC SEtup, Boot SPI");
570
571 SETUP_IOMUX_PADS(usdhc3_pads);
572 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
573 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
574 usdhc_cfg[0].max_bus_width = 4;
575 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
576
577 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
578 }
579
580
board_boot_order(u32 * spl_boot_list)581 void board_boot_order(u32 *spl_boot_list)
582 {
583 spl_boot_list[0] = spl_boot_device();
584 printf("Boot device %x\n", spl_boot_list[0]);
585 switch (spl_boot_list[0]) {
586 case BOOT_DEVICE_SPI:
587 spl_boot_list[1] = BOOT_DEVICE_UART;
588 break;
589 case BOOT_DEVICE_MMC1:
590 spl_boot_list[1] = BOOT_DEVICE_SPI;
591 spl_boot_list[2] = BOOT_DEVICE_UART;
592 break;
593 default:
594 printf("Boot device %x\n", spl_boot_list[0]);
595 }
596 }
597
598 /*
599 * This is used because get_ram_size() does not
600 * take care of cache, resulting a wrong size
601 * pfla02 has just 1, 2 or 4 GB option
602 * Function checks for mirrors in the first CS
603 */
604 #define RAM_TEST_PATTERN 0xaa5555aa
605 #define MIN_BANK_SIZE (512 * 1024 * 1024)
606
pfla02_detect_chiptype(void)607 static unsigned int pfla02_detect_chiptype(void)
608 {
609 u32 *p, *p1;
610 unsigned int offset = MIN_BANK_SIZE;
611 int i;
612
613 for (i = 0; i < 2; i++) {
614 p = (u32 *)PHYS_SDRAM;
615 p1 = (u32 *)(PHYS_SDRAM + (i + 1) * offset);
616
617 *p1 = 0;
618 *p = RAM_TEST_PATTERN;
619
620 /*
621 * This is required to detect mirroring
622 * else we read back values from cache
623 */
624 flush_dcache_all();
625
626 if (*p == *p1)
627 return i;
628 }
629 return RAM_MT256K;
630 }
631
board_init_f(ulong dummy)632 void board_init_f(ulong dummy)
633 {
634 unsigned int ramchip;
635
636 struct mx6_ddr_sysinfo sysinfo = {
637 /* width of data bus:0=16,1=32,2=64 */
638 .dsize = 2,
639 /* config for full 4GB range so that get_mem_size() works */
640 .cs_density = 32, /* 512 MB */
641 /* single chip select */
642 #if IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
643 .ncs = 1,
644 #else
645 .ncs = 2,
646 #endif
647 .cs1_mirror = 1,
648 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
649 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
650 .walat = 1, /* Write additional latency */
651 .ralat = 5, /* Read additional latency */
652 .mif3_mode = 3, /* Command prediction working mode */
653 .bi_on = 1, /* Bank interleaving enabled */
654 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
655 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
656 .ddr_type = DDR_TYPE_DDR3,
657 .refsel = 1, /* Refresh cycles at 32KHz */
658 .refr = 7, /* 8 refresh commands per refresh cycle */
659 };
660
661 #if defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD)
662 /* Enable NAND */
663 setup_gpmi_nand();
664 #endif
665
666 /* setup clock gating */
667 ccgr_init();
668
669 /* setup AIPS and disable watchdog */
670 arch_cpu_init();
671
672 /* setup AXI */
673 gpr_init();
674
675 board_early_init_f();
676
677 /* setup GP timer */
678 timer_init();
679
680 /* UART clocks enabled and gd valid - init serial console */
681 preloader_console_init();
682
683 setup_spi();
684
685 setup_gpios();
686
687 /* DDR initialization */
688 spl_dram_init(&sysinfo, &mt41k_xx[RAM_MT256K]);
689 ramchip = pfla02_detect_chiptype();
690 debug("Detected chip %d\n", ramchip);
691 #if !IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
692 switch (ramchip) {
693 case RAM_MT64K:
694 sysinfo.cs_density = 6;
695 break;
696 case RAM_MT128K:
697 sysinfo.cs_density = 10;
698 break;
699 case RAM_MT256K:
700 sysinfo.cs_density = 18;
701 break;
702 }
703 #endif
704 spl_dram_init(&sysinfo, &mt41k_xx[ramchip]);
705
706 /* Clear the BSS. */
707 memset(__bss_start, 0, __bss_end - __bss_start);
708
709 phyflex_err006282_workaround();
710
711 /* load/boot image from boot device */
712 board_init_r(NULL, 0);
713 }
714 #endif
715