1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * mux.c
4 *
5 * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
6 * Copyright (C) 2019 DENX Software Engineering GmbH
7 */
8
9 #include <common.h>
10 #include <asm/arch/sys_proto.h>
11 #include <asm/arch/hardware.h>
12 #include <asm/arch/mux.h>
13 #include <asm/io.h>
14 #include "board.h"
15
16 static struct module_pin_mux uart0_pin_mux[] = {
17 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
18 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
19 {-1},
20 };
21
22 #ifdef CONFIG_MMC
23 static struct module_pin_mux mmc0_pin_mux[] = {
24 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
25 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
26 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
27 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
28 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
29 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
30 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
31 {-1},
32 };
33 #endif
34
35 static struct module_pin_mux i2c0_pin_mux[] = {
36 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
37 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
38 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
39 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
40 {-1},
41 };
42
43 #ifdef CONFIG_SPI
44 static struct module_pin_mux spi0_pin_mux[] = {
45 {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
46 {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
47 PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
48 {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
49 {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
50 PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
51 {-1},
52 };
53 #endif
54
55 static struct module_pin_mux rmii1_pin_mux[] = {
56 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
57 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
58 {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
59 {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
60 {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
61 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
62 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
63 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
64 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
65 {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
66 {-1},
67 };
68
69 static struct module_pin_mux cbmux_pin_mux[] = {
70 {OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLDOWN_EN}, /* JP3 */
71 {OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUP_EN}, /* JP4 */
72 {-1},
73 };
74
75 #ifdef CONFIG_MTD_RAW_NAND
76 static struct module_pin_mux nand_pin_mux[] = {
77 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
78 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
79 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
80 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
81 {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
82 {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
83 {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
84 {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
85 {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
86 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
87 {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
88 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
89 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
90 {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
91 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
92 {-1},
93 };
94 #endif
95
enable_uart0_pin_mux(void)96 void enable_uart0_pin_mux(void)
97 {
98 configure_module_pin_mux(uart0_pin_mux);
99 }
100
enable_i2c0_pin_mux(void)101 void enable_i2c0_pin_mux(void)
102 {
103 configure_module_pin_mux(i2c0_pin_mux);
104 }
105
enable_board_pin_mux(void)106 void enable_board_pin_mux(void)
107 {
108 configure_module_pin_mux(rmii1_pin_mux);
109 configure_module_pin_mux(mmc0_pin_mux);
110 configure_module_pin_mux(cbmux_pin_mux);
111 #ifdef CONFIG_MTD_RAW_NAND
112 configure_module_pin_mux(nand_pin_mux);
113 #endif
114 #ifdef CONFIG_SPI
115 configure_module_pin_mux(spi0_pin_mux);
116 #endif
117 }
118