1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 */
6
7 #include <common.h>
8 #include <asm/arch/clock.h>
9 #include <asm/arch/ddr.h>
10 #include <asm/arch/imx8mm_pins.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/global_data.h>
13 #include <asm/mach-imx/boot_mode.h>
14 #include <asm/mach-imx/iomux-v3.h>
15 #include <dm/device.h>
16 #include <dm/uclass.h>
17 #include <hang.h>
18 #include <init.h>
19 #include <log.h>
20 #include <spl.h>
21
22 DECLARE_GLOBAL_DATA_PTR;
23
spl_board_boot_device(enum boot_device boot_dev_spl)24 int spl_board_boot_device(enum boot_device boot_dev_spl)
25 {
26 switch (boot_dev_spl) {
27 case SD2_BOOT:
28 case MMC2_BOOT:
29 return BOOT_DEVICE_MMC1;
30 case SD3_BOOT:
31 case MMC3_BOOT:
32 return BOOT_DEVICE_MMC2;
33 case QSPI_BOOT:
34 return BOOT_DEVICE_NOR;
35 case USB_BOOT:
36 return BOOT_DEVICE_BOARD;
37 default:
38 return BOOT_DEVICE_NONE;
39 }
40 }
41
spl_dram_init(void)42 void spl_dram_init(void)
43 {
44 ddr_init(&dram_timing);
45 }
46
spl_board_init(void)47 void spl_board_init(void)
48 {
49 /* Serial download mode */
50 if (is_usb_boot()) {
51 puts("Back to ROM, SDP\n");
52 restore_boot_params();
53 }
54 puts("Normal Boot\n");
55 }
56
57 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)58 int board_fit_config_name_match(const char *name)
59 {
60 /* Just empty function now - can't decide what to choose */
61 debug("%s: %s\n", __func__, name);
62
63 return 0;
64 }
65 #endif
66
67 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
68 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE)
69
70 static iomux_v3_cfg_t const uart_pads[] = {
71 IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
72 IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
73 };
74
75 static iomux_v3_cfg_t const wdog_pads[] = {
76 IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
77 };
78
board_early_init_f(void)79 int board_early_init_f(void)
80 {
81 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
82
83 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
84
85 set_wdog_reset(wdog);
86
87 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
88
89 return 0;
90 }
91
board_init_f(ulong dummy)92 void board_init_f(ulong dummy)
93 {
94 struct udevice *dev;
95 int ret;
96
97 arch_cpu_init();
98
99 init_uart_clk(2);
100
101 board_early_init_f();
102
103 timer_init();
104
105 preloader_console_init();
106
107 /* Clear the BSS. */
108 memset(__bss_start, 0, __bss_end - __bss_start);
109
110 ret = spl_early_init();
111 if (ret) {
112 debug("spl_early_init() failed: %d\n", ret);
113 hang();
114 }
115
116 ret = uclass_get_device_by_name(UCLASS_CLK,
117 "clock-controller@30380000", &dev);
118 if (ret < 0) {
119 printf("Failed to find clock node. Check device tree\n");
120 hang();
121 }
122
123 enable_tzc380();
124
125 /* DDR initialization */
126 spl_dram_init();
127
128 board_init_r(NULL, 0);
129 }
130