1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * board/renesas/blanche/blanche.c
4 * This file is blanche board support.
5 *
6 * Copyright (C) 2016 Renesas Electronics Corporation
7 */
8
9 #include <common.h>
10 #include <cpu_func.h>
11 #include <init.h>
12 #include <net.h>
13 #include <asm/arch/mmc.h>
14 #include <asm/arch/rcar-mstp.h>
15 #include <asm/arch/rmobile.h>
16 #include <asm/arch/sh_sdhi.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/global_data.h>
19 #include <asm/gpio.h>
20 #include <asm/io.h>
21 #include <asm/mach-types.h>
22 #include <asm/processor.h>
23 #include <dm.h>
24 #include <dm/platform_data/serial_sh.h>
25 #include <env.h>
26 #include <hang.h>
27 #include <i2c.h>
28 #include <linux/bitops.h>
29 #include <linux/errno.h>
30 #include <malloc.h>
31 #include <miiphy.h>
32 #include <mmc.h>
33 #include <netdev.h>
34 #include "qos.h"
35
36 DECLARE_GLOBAL_DATA_PTR;
37
38 #define CPG_PLL1CR 0xE6150028
39 #define CPG_PLL3CR 0xE61500DC
40
41 #define TMU0_MSTP125 BIT(25)
42 #define QSPI_MSTP917 BIT(17)
43
44 struct reg_config {
45 u16 off;
46 u32 val;
47 };
48
blanche_init_sys(void)49 static void blanche_init_sys(void)
50 {
51 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
52 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
53 u32 cpu_type;
54
55 cpu_type = rmobile_get_cpu_type();
56 if (cpu_type == 0x4A) {
57 writel(0x4D000000, CPG_PLL1CR);
58 writel(0x4F000000, CPG_PLL3CR);
59 }
60
61 /* Watchdog init */
62 writel(0xA5A5A500, &rwdt->rwtcsra);
63 writel(0xA5A5A500, &swdt->swtcsra);
64 }
65
blanche_init_pfc(void)66 static void blanche_init_pfc(void)
67 {
68 static const struct reg_config pfc_with_unlock[] = {
69 { 0x0004, 0x0bffffff },
70 { 0x0008, 0x002fffff },
71 { 0x0014, 0x00000fff },
72 { 0x0018, 0x00010fff },
73 { 0x001c, 0x00010fff },
74 { 0x0020, 0x00010fff },
75 { 0x0024, 0x00010fff },
76 { 0x0028, 0x00010fff },
77 { 0x002c, 0x04006000 },
78 { 0x0030, 0x303fefe0 },
79 { 0x0058, 0x0002000e },
80 };
81
82 static const struct reg_config pfc_without_unlock[] = {
83 { 0x0108, 0x00000000 },
84 { 0x010c, 0x0803FF40 },
85 { 0x0110, 0x0000FFFF },
86 { 0x0114, 0x00010FFF },
87 { 0x011c, 0x0001AFFF },
88 { 0x0124, 0x0001CFFF },
89 { 0x0128, 0xC0438001 },
90 { 0x012c, 0x0FC00007 },
91 };
92
93 static const u32 pfc_base = 0xe6060000;
94
95 unsigned int i;
96
97 for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
98 writel(~pfc_with_unlock[i].val, pfc_base);
99 writel(pfc_with_unlock[i].val,
100 pfc_base | pfc_with_unlock[i].off);
101 }
102
103 for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
104 writel(pfc_without_unlock[i].val,
105 pfc_base | pfc_without_unlock[i].off);
106 }
107
blanche_init_lbsc(void)108 static void blanche_init_lbsc(void)
109 {
110 static const struct reg_config lbsc_config[] = {
111 { 0x00, 0x00000020 },
112 { 0x08, 0x00002020 },
113 { 0x30, 0x2a103320 },
114 { 0x38, 0x19102110 },
115 };
116
117 static const u32 lbsc_base = 0xfec00200;
118
119 unsigned int i;
120
121 for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
122 writel(lbsc_config[i].val,
123 lbsc_base | lbsc_config[i].off);
124 writel(lbsc_config[i].val,
125 lbsc_base | (lbsc_config[i].off + 4));
126 }
127 }
128
129 #if defined(CONFIG_MTD_NOR_FLASH)
dbsc_wait(u16 reg)130 static void dbsc_wait(u16 reg)
131 {
132 static const u32 dbsc3_0_base = DBSC3_0_BASE;
133
134 while (!(readl(dbsc3_0_base + reg) & BIT(0)))
135 ;
136 }
137
blanche_init_dbsc(void)138 static void blanche_init_dbsc(void)
139 {
140 static const struct reg_config dbsc_config1[] = {
141 { 0x0280, 0x0000a55a },
142 { 0x0018, 0x21000000 },
143 { 0x0018, 0x11000000 },
144 { 0x0018, 0x10000000 },
145 { 0x0290, 0x00000001 },
146 { 0x02a0, 0x80000000 },
147 { 0x0290, 0x00000004 },
148 };
149
150 static const struct reg_config dbsc_config2[] = {
151 { 0x0290, 0x00000006 },
152 { 0x02a0, 0x0001c000 },
153 };
154
155 static const struct reg_config dbsc_config4[] = {
156 { 0x0290, 0x0000000f },
157 { 0x02a0, 0x00181ee4 },
158 { 0x0290, 0x00000010 },
159 { 0x02a0, 0xf00464db },
160 { 0x0290, 0x00000061 },
161 { 0x02a0, 0x0000008d },
162 { 0x0290, 0x00000001 },
163 { 0x02a0, 0x00000073 },
164 { 0x0020, 0x00000007 },
165 { 0x0024, 0x0f030a02 },
166 { 0x0030, 0x00000001 },
167 { 0x00b0, 0x00000000 },
168 { 0x0040, 0x0000000b },
169 { 0x0044, 0x00000008 },
170 { 0x0048, 0x00000000 },
171 { 0x0050, 0x0000000b },
172 { 0x0054, 0x000c000b },
173 { 0x0058, 0x00000027 },
174 { 0x005c, 0x0000001c },
175 { 0x0060, 0x00000006 },
176 { 0x0064, 0x00000020 },
177 { 0x0068, 0x00000008 },
178 { 0x006c, 0x0000000c },
179 { 0x0070, 0x00000009 },
180 { 0x0074, 0x00000012 },
181 { 0x0078, 0x000000d0 },
182 { 0x007c, 0x00140005 },
183 { 0x0080, 0x00050004 },
184 { 0x0084, 0x70233005 },
185 { 0x0088, 0x000c0000 },
186 { 0x008c, 0x00000300 },
187 { 0x0090, 0x00000040 },
188 { 0x0100, 0x00000001 },
189 { 0x00c0, 0x00020001 },
190 { 0x00c8, 0x20082004 },
191 { 0x0380, 0x00020002 },
192 { 0x0390, 0x0000001f },
193 };
194
195 static const struct reg_config dbsc_config5[] = {
196 { 0x0244, 0x00000011 },
197 { 0x0290, 0x00000003 },
198 { 0x02a0, 0x0300c4e1 },
199 { 0x0290, 0x00000023 },
200 { 0x02a0, 0x00fcdb60 },
201 { 0x0290, 0x00000011 },
202 { 0x02a0, 0x1000040b },
203 { 0x0290, 0x00000012 },
204 { 0x02a0, 0x9d9cbb66 },
205 { 0x0290, 0x00000013 },
206 { 0x02a0, 0x1a868400 },
207 { 0x0290, 0x00000014 },
208 { 0x02a0, 0x300214d8 },
209 { 0x0290, 0x00000015 },
210 { 0x02a0, 0x00000d70 },
211 { 0x0290, 0x00000016 },
212 { 0x02a0, 0x00000004 },
213 { 0x0290, 0x00000017 },
214 { 0x02a0, 0x00000018 },
215 { 0x0290, 0x0000001a },
216 { 0x02a0, 0x910035c7 },
217 { 0x0290, 0x00000004 },
218 };
219
220 static const struct reg_config dbsc_config6[] = {
221 { 0x0290, 0x00000001 },
222 { 0x02a0, 0x00000181 },
223 { 0x0018, 0x11000000 },
224 { 0x0290, 0x00000004 },
225 };
226
227 static const struct reg_config dbsc_config7[] = {
228 { 0x0290, 0x00000001 },
229 { 0x02a0, 0x0000fe01 },
230 { 0x0304, 0x00000000 },
231 { 0x00f4, 0x01004c20 },
232 { 0x00f8, 0x014000aa },
233 { 0x00e0, 0x00000140 },
234 { 0x00e4, 0x00081860 },
235 { 0x00e8, 0x00010000 },
236 { 0x0290, 0x00000004 },
237 };
238
239 static const struct reg_config dbsc_config8[] = {
240 { 0x0014, 0x00000001 },
241 { 0x0010, 0x00000001 },
242 { 0x0280, 0x00000000 },
243 };
244
245 static const u32 dbsc3_0_base = DBSC3_0_BASE;
246 unsigned int i;
247
248 for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
249 writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
250
251 dbsc_wait(0x2a0);
252
253 for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
254 writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
255
256 for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
257 writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
258
259 dbsc_wait(0x240);
260
261 for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
262 writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
263
264 dbsc_wait(0x2a0);
265
266 for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
267 writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
268
269 dbsc_wait(0x2a0);
270
271 for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
272 writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
273
274 dbsc_wait(0x2a0);
275
276 for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
277 writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
278
279 }
280
s_init_wait(volatile unsigned int cnt)281 static void s_init_wait(volatile unsigned int cnt)
282 {
283 volatile u32 i = cnt * 0x10000;
284
285 while (i-- > 0)
286 ;
287 }
288 #endif
289
s_init(void)290 void s_init(void)
291 {
292 blanche_init_sys();
293 qos_init();
294 blanche_init_pfc();
295 blanche_init_lbsc();
296 #if defined(CONFIG_MTD_NOR_FLASH)
297 s_init_wait(10);
298 blanche_init_dbsc();
299 #endif /* CONFIG_MTD_NOR_FLASH */
300 }
301
board_early_init_f(void)302 int board_early_init_f(void)
303 {
304 /* TMU0 */
305 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
306 /* QSPI */
307 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
308
309 return 0;
310 }
311
board_init(void)312 int board_init(void)
313 {
314 /* adress of boot parameters */
315 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
316
317 return 0;
318 }
319
320 /* Added for BLANCHE(R-CarV2H board) */
321 #ifndef CONFIG_DM_ETH
board_eth_init(struct bd_info * bis)322 int board_eth_init(struct bd_info *bis)
323 {
324 int rc = 0;
325
326 #ifdef CONFIG_SMC911X
327 struct eth_device *dev;
328 uchar eth_addr[6];
329
330 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
331
332 if (!eth_env_get_enetaddr("ethaddr", eth_addr)) {
333 dev = eth_get_dev_by_index(0);
334 if (dev) {
335 eth_env_set_enetaddr("ethaddr", dev->enetaddr);
336 } else {
337 printf("blanche: Couldn't get eth device\n");
338 rc = -1;
339 }
340 }
341
342 #endif
343
344 return rc;
345 }
346 #endif
347
dram_init(void)348 int dram_init(void)
349 {
350 if (fdtdec_setup_mem_size_base() != 0)
351 return -EINVAL;
352
353 return 0;
354 }
355
dram_init_banksize(void)356 int dram_init_banksize(void)
357 {
358 fdtdec_setup_memory_banksize();
359
360 return 0;
361 }
362
reset_cpu(ulong addr)363 void reset_cpu(ulong addr)
364 {
365 struct udevice *dev;
366 const u8 pmic_bus = 6;
367 const u8 pmic_addr = 0x58;
368 u8 data;
369 int ret;
370
371 ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
372 if (ret)
373 hang();
374
375 ret = dm_i2c_read(dev, 0x13, &data, 1);
376 if (ret)
377 hang();
378
379 data |= BIT(1);
380
381 ret = dm_i2c_write(dev, 0x13, &data, 1);
382 if (ret)
383 hang();
384 }
385