1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * board/renesas/draak/draak.c
4  *     This file is Draak board support.
5  *
6  * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
7  */
8 
9 #include <common.h>
10 #include <cpu_func.h>
11 #include <hang.h>
12 #include <init.h>
13 #include <malloc.h>
14 #include <netdev.h>
15 #include <dm.h>
16 #include <asm/global_data.h>
17 #include <dm/platform_data/serial_sh.h>
18 #include <asm/processor.h>
19 #include <asm/mach-types.h>
20 #include <asm/io.h>
21 #include <linux/bitops.h>
22 #include <linux/errno.h>
23 #include <asm/arch/sys_proto.h>
24 #include <asm/gpio.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/arch/rmobile.h>
27 #include <asm/arch/rcar-mstp.h>
28 #include <asm/arch/sh_sdhi.h>
29 #include <i2c.h>
30 #include <mmc.h>
31 
32 DECLARE_GLOBAL_DATA_PTR;
33 
34 #define GSX_MSTP112		BIT(12)	/* 3DG */
35 #define SCIF2_MSTP310		BIT(10)	/* SCIF2 */
36 #define DVFS_MSTP926		BIT(26)
37 #define HSUSB_MSTP704		BIT(4)	/* HSUSB */
38 
board_early_init_f(void)39 int board_early_init_f(void)
40 {
41 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
42 	/* DVFS for reset */
43 	mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
44 #endif
45 	return 0;
46 }
47 
48 /* HSUSB block registers */
49 #define HSUSB_REG_LPSTS			0xE6590102
50 #define HSUSB_REG_LPSTS_SUSPM_NORMAL	BIT(14)
51 #define HSUSB_REG_UGCTRL2		0xE6590184
52 #define HSUSB_REG_UGCTRL2_USB0SEL	0x30
53 #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI	0x10
54 
board_init(void)55 int board_init(void)
56 {
57 	/* adress of boot parameters */
58 	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
59 
60 	/* USB1 pull-up */
61 	setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
62 
63 	/* Configure the HSUSB block */
64 	mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
65 	/* Choice USB0SEL */
66 	clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
67 			HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
68 	/* low power status */
69 	setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
70 
71 	return 0;
72 }
73 
74 #define RST_BASE	0xE6160000
75 #define RST_CA53RESCNT	(RST_BASE + 0x44)
76 #define RST_CA53_CODE	0x5A5A000F
77 
reset_cpu(ulong addr)78 void reset_cpu(ulong addr)
79 {
80 	writel(RST_CA53_CODE, RST_CA53RESCNT);
81 }
82