1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2017 Renesas Electronics
4 * Copyright (C) 2017 Chris Brandt
5 */
6#include <config.h>
7#include <version.h>
8#include <asm/macro.h>
9
10/* Watchdog Registers */
11#define RZA1_WDT_BASE	0xFCFE0000
12#define WTCSR	(RZA1_WDT_BASE + 0x00) /* Watchdog Timer Control Register */
13#define WTCNT	(RZA1_WDT_BASE + 0x02) /* Watchdog Timer Counter Register */
14#define WRCSR	(RZA1_WDT_BASE + 0x04) /* Watchdog Reset Control Register */
15
16/* Standby controller registers (chapter 55) */
17#define RZA1_STBCR_BASE	0xFCFE0020
18#define STBCR1	(RZA1_STBCR_BASE + 0x00)
19#define STBCR2	(RZA1_STBCR_BASE + 0x04)
20#define STBCR3	(RZA1_STBCR_BASE + 0x400)
21#define STBCR4	(RZA1_STBCR_BASE + 0x404)
22#define STBCR5	(RZA1_STBCR_BASE + 0x408)
23#define STBCR6	(RZA1_STBCR_BASE + 0x40c)
24#define STBCR7	(RZA1_STBCR_BASE + 0x410)
25#define STBCR8	(RZA1_STBCR_BASE + 0x414)
26#define STBCR9	(RZA1_STBCR_BASE + 0x418)
27#define STBCR10	(RZA1_STBCR_BASE + 0x41c)
28#define STBCR11	(RZA1_STBCR_BASE + 0x420)
29#define STBCR12	(RZA1_STBCR_BASE + 0x424)
30#define STBCR13	(RZA1_STBCR_BASE + 0x450)
31
32/* Clock Registers */
33#define RZA1_FRQCR_BASE	0xFCFE0010
34#define FRQCR	(RZA1_FRQCR_BASE + 0x00)
35#define FRQCR2	(RZA1_FRQCR_BASE + 0x04)
36
37#define SYSCR1	0xFCFE0400 /* System control register 1 */
38#define SYSCR2	0xFCFE0404 /* System control register 2 */
39#define SYSCR3	0xFCFE0408 /* System control register 3 */
40
41/* Disable WDT */
42#define WTCSR_D		0xA518
43#define WTCNT_D		0x5A00
44
45/* Enable all peripheral clocks */
46#define STBCR3_D	0x00000000
47#define STBCR4_D	0x00000000
48#define STBCR5_D	0x00000000
49#define STBCR6_D	0x00000000
50#define STBCR7_D	0x00000024
51#define STBCR8_D	0x00000005
52#define STBCR9_D	0x00000000
53#define STBCR10_D	0x00000000
54#define STBCR11_D	0x000000c0
55#define STBCR12_D	0x000000f0
56
57/*
58 * Set all system clocks to full speed.
59 * On reset, the CPU will be running at 1/2 speed.
60 * In the Hardware Manual, see Table 6.3 Settable Frequency Ranges
61 */
62#define FRQCR_D		0x0035
63#define FRQCR2_D	0x0001
64
65	.global	lowlevel_init
66
67	.text
68	.align	2
69
70lowlevel_init:
71	/* PL310 init */
72	write32 0x3fffff80, 0x00000001
73
74	/* Disable WDT */
75	write16	WTCSR, WTCSR_D
76	write16	WTCNT, WTCNT_D
77
78	/* Set clocks */
79	write16	FRQCR, FRQCR_D
80	write16	FRQCR2, FRQCR2_D
81
82	/* Enable all peripherals(Standby Control) */
83	write8 STBCR3, STBCR3_D
84	write8 STBCR4, STBCR4_D
85	write8 STBCR5, STBCR5_D
86	write8 STBCR6, STBCR6_D
87	write8 STBCR7, STBCR7_D
88	write8 STBCR8, STBCR8_D
89	write8 STBCR9, STBCR9_D
90	write8 STBCR10, STBCR10_D
91	write8 STBCR11, STBCR11_D
92	write8 STBCR12, STBCR12_D
93
94	/* For serial booting, enable read ahead caching to speed things up */
95#define DRCR_0  0x3FEFA00C
96	write32 DRCR_0, 0x00010100	/* Read Burst ON, Length=2 */
97
98	/* Enable all internal RAM */
99	write8 SYSCR1, 0xFF
100	write8 SYSCR2, 0xFF
101	write8 SYSCR3, 0xFF
102
103	nop
104	/* back to arch calling code */
105	mov	pc, lr
106
107	.align 4
108