1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * board/renesas/silk/silk_spl.c
4 *
5 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
6 */
7
8 #include <common.h>
9 #include <cpu_func.h>
10 #include <init.h>
11 #include <malloc.h>
12 #include <dm/platform_data/serial_sh.h>
13 #include <asm/processor.h>
14 #include <asm/mach-types.h>
15 #include <asm/io.h>
16 #include <linux/bitops.h>
17 #include <linux/errno.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/gpio.h>
20 #include <asm/arch/rmobile.h>
21 #include <asm/arch/rcar-mstp.h>
22
23 #include <spl.h>
24
25 #define TMU0_MSTP125 BIT(25)
26 #define SCIF2_MSTP719 BIT(19)
27 #define QSPI_MSTP917 BIT(17)
28
29 #define SD1CKCR 0xE6150078
30 #define SD_97500KHZ 0x7
31
32 struct reg_config {
33 u16 off;
34 u32 val;
35 };
36
dbsc_wait(u16 reg)37 static void dbsc_wait(u16 reg)
38 {
39 static const u32 dbsc3_0_base = DBSC3_0_BASE;
40
41 while (!(readl(dbsc3_0_base + reg) & BIT(0)))
42 ;
43 }
44
spl_init_sys(void)45 static void spl_init_sys(void)
46 {
47 u32 r0 = 0;
48
49 writel(0xa5a5a500, 0xe6020004);
50 writel(0xa5a5a500, 0xe6030004);
51
52 asm volatile(
53 /* ICIALLU - Invalidate I$ to PoU */
54 "mcr 15, 0, %0, cr7, cr5, 0 \n"
55 /* BPIALL - Invalidate branch predictors */
56 "mcr 15, 0, %0, cr7, cr5, 6 \n"
57 /* Set SCTLR[IZ] */
58 "mrc 15, 0, %0, cr1, cr0, 0 \n"
59 "orr %0, #0x1800 \n"
60 "mcr 15, 0, %0, cr1, cr0, 0 \n"
61 "isb sy \n"
62 :"=r"(r0));
63 }
64
spl_init_pfc(void)65 static void spl_init_pfc(void)
66 {
67 static const struct reg_config pfc_with_unlock[] = {
68 { 0x0090, 0x00018040 },
69 { 0x0094, 0x00000000 },
70 { 0x0098, 0x00000000 },
71 { 0x0020, 0x94000000 },
72 { 0x0024, 0x00000006 },
73 { 0x0028, 0x40000000 },
74 { 0x002c, 0x00000155 },
75 { 0x0030, 0x00000002 },
76 { 0x0034, 0x00000000 },
77 { 0x0038, 0x00000000 },
78 { 0x003c, 0x00000000 },
79 { 0x0040, 0x60000000 },
80 { 0x0044, 0x36dab6db },
81 { 0x0048, 0x926da012 },
82 { 0x004c, 0x0008c383 },
83 { 0x0050, 0x00000000 },
84 { 0x0054, 0x00000140 },
85 { 0x0004, 0xffffffff },
86 { 0x0008, 0x00ec3fff },
87 { 0x000c, 0x5bffffff },
88 { 0x0010, 0x01bfe1ff },
89 { 0x0014, 0x5bffffff },
90 { 0x0018, 0x0f4b200f },
91 { 0x001c, 0x03ffffff },
92 };
93
94 static const struct reg_config pfc_without_unlock[] = {
95 { 0x0100, 0x00000000 },
96 { 0x0104, 0x4203fdf0 },
97 { 0x0108, 0x00000000 },
98 { 0x010c, 0x159007ff },
99 { 0x0110, 0x80000000 },
100 { 0x0114, 0x00de481f },
101 { 0x0118, 0x00000000 },
102 };
103
104 static const struct reg_config pfc_with_unlock2[] = {
105 { 0x0060, 0xffffffff },
106 { 0x0064, 0xfffff000 },
107 { 0x0068, 0x55555500 },
108 { 0x006c, 0xffffff00 },
109 { 0x0070, 0x00000000 },
110 };
111
112 static const u32 pfc_base = 0xe6060000;
113
114 unsigned int i;
115
116 for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
117 writel(~pfc_with_unlock[i].val, pfc_base);
118 writel(pfc_with_unlock[i].val,
119 pfc_base | pfc_with_unlock[i].off);
120 }
121
122 for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
123 writel(pfc_without_unlock[i].val,
124 pfc_base | pfc_without_unlock[i].off);
125
126 for (i = 0; i < ARRAY_SIZE(pfc_with_unlock2); i++) {
127 writel(~pfc_with_unlock2[i].val, pfc_base);
128 writel(pfc_with_unlock2[i].val,
129 pfc_base | pfc_with_unlock2[i].off);
130 }
131 }
132
spl_init_gpio(void)133 static void spl_init_gpio(void)
134 {
135 static const u16 gpio_offs[] = {
136 0x1000, 0x2000, 0x3000, 0x4000
137 };
138
139 static const struct reg_config gpio_set[] = {
140 { 0x2000, 0x24000000 },
141 { 0x4000, 0xa4000000 },
142 { 0x5000, 0x0084c000 },
143 };
144
145 static const struct reg_config gpio_clr[] = {
146 { 0x1000, 0x01000000 },
147 { 0x2000, 0x24000000 },
148 { 0x3000, 0x00000000 },
149 { 0x4000, 0xa4000000 },
150 { 0x5000, 0x00044380 },
151 };
152
153 static const u32 gpio_base = 0xe6050000;
154
155 unsigned int i;
156
157 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
158 writel(0, gpio_base | 0x20 | gpio_offs[i]);
159 writel(BIT(23), gpio_base | 0x5020);
160
161 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
162 writel(0, gpio_base | 0x00 | gpio_offs[i]);
163 writel(BIT(23), gpio_base | 0x5000);
164
165 for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
166 writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
167
168 for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
169 writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
170 }
171
spl_init_lbsc(void)172 static void spl_init_lbsc(void)
173 {
174 static const struct reg_config lbsc_config[] = {
175 { 0x00, 0x00000020 },
176 { 0x08, 0x00002020 },
177 { 0x30, 0x2a103320 },
178 { 0x38, 0xff70ff70 },
179 };
180
181 static const u16 lbsc_offs[] = {
182 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8
183 };
184
185 static const u32 lbsc_base = 0xfec00200;
186
187 unsigned int i;
188
189 for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
190 writel(lbsc_config[i].val,
191 lbsc_base | lbsc_config[i].off);
192 writel(lbsc_config[i].val,
193 lbsc_base | (lbsc_config[i].off + 4));
194 }
195
196 for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
197 writel(0, lbsc_base | lbsc_offs[i]);
198 }
199
spl_init_dbsc(void)200 static void spl_init_dbsc(void)
201 {
202 static const struct reg_config dbsc_config1[] = {
203 { 0x0018, 0x21000000 },
204 { 0x0018, 0x11000000 },
205 { 0x0018, 0x10000000 },
206 { 0x0280, 0x0000a55a },
207 { 0x0290, 0x00000001 },
208 { 0x02a0, 0x80000000 },
209 { 0x0290, 0x00000004 },
210 };
211
212 static const struct reg_config dbsc_config2[] = {
213 { 0x0290, 0x00000006 },
214 { 0x02a0, 0x0005c000 },
215 };
216
217 static const struct reg_config dbsc_config3r2[] = {
218 { 0x0290, 0x0000000f },
219 { 0x02a0, 0x00181224 },
220 };
221
222 static const struct reg_config dbsc_config4[] = {
223 { 0x0290, 0x00000010 },
224 { 0x02a0, 0xf004649b },
225 { 0x0290, 0x00000061 },
226 { 0x02a0, 0x0000006d },
227 { 0x0290, 0x00000001 },
228 { 0x02a0, 0x00000073 },
229 { 0x0020, 0x00000007 },
230 { 0x0024, 0x0f030a02 },
231 { 0x0030, 0x00000001 },
232 { 0x00b0, 0x00000000 },
233 { 0x0040, 0x00000009 },
234 { 0x0044, 0x00000007 },
235 { 0x0048, 0x00000000 },
236 { 0x0050, 0x00000009 },
237 { 0x0054, 0x000a0009 },
238 { 0x0058, 0x00000021 },
239 { 0x005c, 0x00000018 },
240 { 0x0060, 0x00000005 },
241 { 0x0064, 0x00000020 },
242 { 0x0068, 0x00000007 },
243 { 0x006c, 0x0000000a },
244 { 0x0070, 0x00000009 },
245 { 0x0074, 0x00000010 },
246 { 0x0078, 0x000000ae },
247 { 0x007c, 0x00140005 },
248 { 0x0080, 0x00050004 },
249 { 0x0084, 0x50213005 },
250 { 0x0088, 0x000c0000 },
251 { 0x008c, 0x00000200 },
252 { 0x0090, 0x00000040 },
253 { 0x0100, 0x00000001 },
254 { 0x00c0, 0x00020001 },
255 { 0x00c8, 0x20042004 },
256 { 0x0380, 0x00020003 },
257 { 0x0390, 0x0000001f },
258 };
259
260 static const struct reg_config dbsc_config5[] = {
261 { 0x0244, 0x00000011 },
262 { 0x0290, 0x00000003 },
263 { 0x02a0, 0x0300c4e1 },
264 { 0x0290, 0x00000023 },
265 { 0x02a0, 0x00fcb6d0 },
266 { 0x0290, 0x00000011 },
267 { 0x02a0, 0x1000040b },
268 { 0x0290, 0x00000012 },
269 { 0x02a0, 0x85589955 },
270 { 0x0290, 0x00000013 },
271 { 0x02a0, 0x1a852400 },
272 { 0x0290, 0x00000014 },
273 { 0x02a0, 0x300210b4 },
274 { 0x0290, 0x00000015 },
275 { 0x02a0, 0x00000b50 },
276 { 0x0290, 0x00000016 },
277 { 0x02a0, 0x00000006 },
278 { 0x0290, 0x00000017 },
279 { 0x02a0, 0x00000010 },
280 { 0x0290, 0x0000001a },
281 { 0x02a0, 0x910035c7 },
282 { 0x0290, 0x00000004 },
283 };
284
285 static const struct reg_config dbsc_config6[] = {
286 { 0x0290, 0x00000001 },
287 { 0x02a0, 0x00000181 },
288 { 0x0018, 0x11000000 },
289 { 0x0290, 0x00000004 },
290 };
291
292 static const struct reg_config dbsc_config7[] = {
293 { 0x0290, 0x00000001 },
294 { 0x02a0, 0x0000fe01 },
295 { 0x0304, 0x00000000 },
296 { 0x00f4, 0x01004c20 },
297 { 0x00f8, 0x012c00be },
298 { 0x00e0, 0x00000140 },
299 { 0x00e4, 0x00081450 },
300 { 0x00e8, 0x00010000 },
301 { 0x0290, 0x00000004 },
302 };
303
304 static const struct reg_config dbsc_config8[] = {
305 { 0x0014, 0x00000001 },
306 { 0x0290, 0x00000010 },
307 { 0x02a0, 0xf00464db },
308 { 0x0010, 0x00000001 },
309 { 0x0280, 0x00000000 },
310 };
311
312 static const u32 dbsc3_0_base = DBSC3_0_BASE;
313 unsigned int i;
314
315 for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
316 writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
317
318 dbsc_wait(0x2a0);
319
320 for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
321 writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
322
323 for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
324 writel(dbsc_config3r2[i].val,
325 dbsc3_0_base | dbsc_config3r2[i].off);
326 }
327
328 for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
329 writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
330
331 dbsc_wait(0x240);
332
333 for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
334 writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
335
336 dbsc_wait(0x2a0);
337
338 for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
339 writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
340
341 dbsc_wait(0x2a0);
342
343 for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
344 writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
345
346 dbsc_wait(0x2a0);
347
348 for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
349 writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
350
351 }
352
spl_init_qspi(void)353 static void spl_init_qspi(void)
354 {
355 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
356
357 static const u32 qspi_base = 0xe6b10000;
358
359 writeb(0x08, qspi_base + 0x00);
360 writeb(0x00, qspi_base + 0x01);
361 writeb(0x06, qspi_base + 0x02);
362 writeb(0x01, qspi_base + 0x0a);
363 writeb(0x00, qspi_base + 0x0b);
364 writeb(0x00, qspi_base + 0x0c);
365 writeb(0x00, qspi_base + 0x0d);
366 writeb(0x00, qspi_base + 0x0e);
367
368 writew(0xe080, qspi_base + 0x10);
369
370 writeb(0xc0, qspi_base + 0x18);
371 writeb(0x00, qspi_base + 0x18);
372 writeb(0x00, qspi_base + 0x08);
373 writeb(0x48, qspi_base + 0x00);
374 }
375
board_init_f(ulong dummy)376 void board_init_f(ulong dummy)
377 {
378 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
379 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
380
381 /* Set SD1 to the 97.5MHz */
382 writel(SD_97500KHZ, SD1CKCR);
383
384 spl_init_sys();
385 spl_init_pfc();
386 spl_init_gpio();
387 spl_init_lbsc();
388 spl_init_dbsc();
389 spl_init_qspi();
390 }
391
spl_board_init(void)392 void spl_board_init(void)
393 {
394 /* UART clocks enabled and gd valid - init serial console */
395 preloader_console_init();
396 }
397
board_boot_order(u32 * spl_boot_list)398 void board_boot_order(u32 *spl_boot_list)
399 {
400 const u32 jtag_magic = 0x1337c0de;
401 const u32 load_magic = 0xb33fc0de;
402
403 /*
404 * If JTAG probe sets special word at 0xe6300020, then it must
405 * put U-Boot into RAM and SPL will start it from RAM.
406 */
407 if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
408 printf("JTAG boot detected!\n");
409
410 while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
411 ;
412
413 spl_boot_list[0] = BOOT_DEVICE_RAM;
414 spl_boot_list[1] = BOOT_DEVICE_NONE;
415
416 return;
417 }
418
419 /* Boot from SPI NOR with YMODEM UART fallback. */
420 spl_boot_list[0] = BOOT_DEVICE_SPI;
421 spl_boot_list[1] = BOOT_DEVICE_UART;
422 spl_boot_list[2] = BOOT_DEVICE_NONE;
423 }
424
reset_cpu(ulong addr)425 void reset_cpu(ulong addr)
426 {
427 }
428