1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Stout board CPLD access support
4 *
5 * Copyright (C) 2015 Renesas Electronics Europe GmbH
6 * Copyright (C) 2015 Renesas Electronics Corporation
7 * Copyright (C) 2015 Cogent Embedded, Inc.
8 */
9
10 #include <common.h>
11 #include <command.h>
12 #include <cpu_func.h>
13 #include <asm/io.h>
14 #include <asm/gpio.h>
15 #include "cpld.h"
16
17 #define SCLK (92 + 24)
18 #define SSTBZ (92 + 25)
19 #define MOSI (92 + 26)
20 #define MISO (92 + 27)
21
22 #define CPLD_ADDR_MODE 0x00 /* RW */
23 #define CPLD_ADDR_MUX 0x01 /* RW */
24 #define CPLD_ADDR_HDMI 0x02 /* RW */
25 #define CPLD_ADDR_DIPSW 0x08 /* R */
26 #define CPLD_ADDR_RESET 0x80 /* RW */
27 #define CPLD_ADDR_VERSION 0xFF /* R */
28
cpld_read(u8 addr)29 static u32 cpld_read(u8 addr)
30 {
31 int i;
32 u32 data = 0;
33
34 for (i = 0; i < 8; i++) {
35 gpio_set_value(MOSI, addr & 0x80); /* MSB first */
36 gpio_set_value(SCLK, 1);
37 addr <<= 1;
38 gpio_set_value(SCLK, 0);
39 }
40
41 gpio_set_value(MOSI, 0); /* READ */
42 gpio_set_value(SSTBZ, 0);
43 gpio_set_value(SCLK, 1);
44 gpio_set_value(SCLK, 0);
45 gpio_set_value(SSTBZ, 1);
46
47 for (i = 0; i < 32; i++) {
48 gpio_set_value(SCLK, 1);
49 data <<= 1;
50 data |= gpio_get_value(MISO); /* MSB first */
51 gpio_set_value(SCLK, 0);
52 }
53
54 return data;
55 }
56
cpld_write(u8 addr,u32 data)57 static void cpld_write(u8 addr, u32 data)
58 {
59 int i;
60
61 for (i = 0; i < 32; i++) {
62 gpio_set_value(MOSI, data & (1 << 31)); /* MSB first */
63 gpio_set_value(SCLK, 1);
64 data <<= 1;
65 gpio_set_value(SCLK, 0);
66 }
67
68 for (i = 0; i < 8; i++) {
69 gpio_set_value(MOSI, addr & 0x80); /* MSB first */
70 gpio_set_value(SCLK, 1);
71 addr <<= 1;
72 gpio_set_value(SCLK, 0);
73 }
74
75 gpio_set_value(MOSI, 1); /* WRITE */
76 gpio_set_value(SSTBZ, 0);
77 gpio_set_value(SCLK, 1);
78 gpio_set_value(SCLK, 0);
79 gpio_set_value(SSTBZ, 1);
80 }
81
82 /* LSI pin pull-up control */
83 #define PUPR3 0xe606010C
84 #define PUPR3_SD3_DAT1 (1 << 27)
85
cpld_init(void)86 void cpld_init(void)
87 {
88 u32 val;
89
90 /* PULL-UP on MISO line */
91 val = readl(PUPR3);
92 val |= PUPR3_SD3_DAT1;
93 writel(val, PUPR3);
94
95 gpio_request(SCLK, "SCLK");
96 gpio_request(SSTBZ, "SSTBZ");
97 gpio_request(MOSI, "MOSI");
98 gpio_request(MISO, "MISO");
99
100 gpio_direction_output(SCLK, 0);
101 gpio_direction_output(SSTBZ, 1);
102 gpio_direction_output(MOSI, 0);
103 gpio_direction_input(MISO);
104
105 /* dummy read */
106 cpld_read(CPLD_ADDR_VERSION);
107
108 printf("CPLD version: 0x%08x\n",
109 cpld_read(CPLD_ADDR_VERSION));
110 printf("H2 Mode setting (MD0..28): 0x%08x\n",
111 cpld_read(CPLD_ADDR_MODE));
112 printf("Multiplexer settings: 0x%08x\n",
113 cpld_read(CPLD_ADDR_MUX));
114 printf("HDMI setting: 0x%08x\n",
115 cpld_read(CPLD_ADDR_HDMI));
116 printf("DIPSW (SW3): 0x%08x\n",
117 cpld_read(CPLD_ADDR_DIPSW));
118
119 #ifdef CONFIG_SH_SDHI
120 /* switch MUX to SD0 */
121 val = cpld_read(CPLD_ADDR_MUX);
122 val &= ~MUX_MSK_SD0;
123 val |= MUX_VAL_SD0;
124 cpld_write(CPLD_ADDR_MUX, val);
125 #endif
126 }
127
do_cpld(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])128 static int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc,
129 char *const argv[])
130 {
131 u32 addr, val;
132
133 if (argc < 3)
134 return CMD_RET_USAGE;
135
136 addr = simple_strtoul(argv[2], NULL, 16);
137 if (!(addr == CPLD_ADDR_VERSION || addr == CPLD_ADDR_MODE ||
138 addr == CPLD_ADDR_MUX || addr == CPLD_ADDR_HDMI ||
139 addr == CPLD_ADDR_DIPSW || addr == CPLD_ADDR_RESET)) {
140 printf("cpld invalid addr\n");
141 return CMD_RET_USAGE;
142 }
143
144 if (argc == 3 && strcmp(argv[1], "read") == 0) {
145 printf("0x%x\n", cpld_read(addr));
146 } else if (argc == 4 && strcmp(argv[1], "write") == 0) {
147 val = simple_strtoul(argv[3], NULL, 16);
148 if (addr == CPLD_ADDR_MUX) {
149 /* never mask SCIFA0 console */
150 val &= ~MUX_MSK_SCIFA0_USB;
151 val |= MUX_VAL_SCIFA0_USB;
152 }
153 cpld_write(addr, val);
154 }
155
156 return 0;
157 }
158
159 U_BOOT_CMD(
160 cpld, 4, 1, do_cpld,
161 "CPLD access",
162 "read addr\n"
163 "cpld write addr val\n"
164 );
165
reset_cpu(ulong addr)166 void reset_cpu(ulong addr)
167 {
168 cpld_write(CPLD_ADDR_RESET, 1);
169 }
170