1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * ULCB board CPLD access support
4 *
5 * Copyright (C) 2017 Renesas Electronics Corporation
6 * Copyright (C) 2017 Cogent Embedded, Inc.
7 */
8
9 #include <common.h>
10 #include <command.h>
11 #include <asm/gpio.h>
12 #include <asm/io.h>
13 #include <dm.h>
14 #include <errno.h>
15 #include <linux/err.h>
16 #include <sysreset.h>
17
18 #define CPLD_ADDR_MODE 0x00 /* RW */
19 #define CPLD_ADDR_MUX 0x02 /* RW */
20 #define CPLD_ADDR_DIPSW6 0x08 /* R */
21 #define CPLD_ADDR_RESET 0x80 /* RW */
22 #define CPLD_ADDR_VERSION 0xFF /* R */
23
24 struct renesas_ulcb_sysreset_priv {
25 struct gpio_desc miso;
26 struct gpio_desc mosi;
27 struct gpio_desc sck;
28 struct gpio_desc sstbz;
29 };
30
cpld_read(struct udevice * dev,u8 addr)31 static u32 cpld_read(struct udevice *dev, u8 addr)
32 {
33 struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
34 u32 data = 0;
35 int i;
36
37 for (i = 0; i < 8; i++) {
38 dm_gpio_set_value(&priv->mosi, !!(addr & 0x80)); /* MSB first */
39 dm_gpio_set_value(&priv->sck, 1);
40 addr <<= 1;
41 dm_gpio_set_value(&priv->sck, 0);
42 }
43
44 dm_gpio_set_value(&priv->mosi, 0); /* READ */
45 dm_gpio_set_value(&priv->sstbz, 0);
46 dm_gpio_set_value(&priv->sck, 1);
47 dm_gpio_set_value(&priv->sck, 0);
48 dm_gpio_set_value(&priv->sstbz, 1);
49
50 for (i = 0; i < 32; i++) {
51 dm_gpio_set_value(&priv->sck, 1);
52 data <<= 1;
53 data |= dm_gpio_get_value(&priv->miso); /* MSB first */
54 dm_gpio_set_value(&priv->sck, 0);
55 }
56
57 return data;
58 }
59
cpld_write(struct udevice * dev,u8 addr,u32 data)60 static void cpld_write(struct udevice *dev, u8 addr, u32 data)
61 {
62 struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
63 int i;
64
65 for (i = 0; i < 32; i++) {
66 dm_gpio_set_value(&priv->mosi, data & (1 << 31)); /* MSB first */
67 dm_gpio_set_value(&priv->sck, 1);
68 data <<= 1;
69 dm_gpio_set_value(&priv->sck, 0);
70 }
71
72 for (i = 0; i < 8; i++) {
73 dm_gpio_set_value(&priv->mosi, addr & 0x80); /* MSB first */
74 dm_gpio_set_value(&priv->sck, 1);
75 addr <<= 1;
76 dm_gpio_set_value(&priv->sck, 0);
77 }
78
79 dm_gpio_set_value(&priv->mosi, 1); /* WRITE */
80 dm_gpio_set_value(&priv->sstbz, 0);
81 dm_gpio_set_value(&priv->sck, 1);
82 dm_gpio_set_value(&priv->sck, 0);
83 dm_gpio_set_value(&priv->sstbz, 1);
84 }
85
do_cpld(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])86 static int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc,
87 char *const argv[])
88 {
89 struct udevice *dev;
90 u32 addr, val;
91 int ret;
92
93 ret = uclass_get_device_by_driver(UCLASS_SYSRESET,
94 DM_DRIVER_GET(sysreset_renesas_ulcb),
95 &dev);
96 if (ret)
97 return ret;
98
99 if (argc == 2 && strcmp(argv[1], "info") == 0) {
100 printf("CPLD version:\t\t\t0x%08x\n",
101 cpld_read(dev, CPLD_ADDR_VERSION));
102 printf("H3 Mode setting (MD0..28):\t0x%08x\n",
103 cpld_read(dev, CPLD_ADDR_MODE));
104 printf("Multiplexer settings:\t\t0x%08x\n",
105 cpld_read(dev, CPLD_ADDR_MUX));
106 printf("DIPSW (SW6):\t\t\t0x%08x\n",
107 cpld_read(dev, CPLD_ADDR_DIPSW6));
108 return 0;
109 }
110
111 if (argc < 3)
112 return CMD_RET_USAGE;
113
114 addr = simple_strtoul(argv[2], NULL, 16);
115 if (!(addr == CPLD_ADDR_VERSION || addr == CPLD_ADDR_MODE ||
116 addr == CPLD_ADDR_MUX || addr == CPLD_ADDR_DIPSW6 ||
117 addr == CPLD_ADDR_RESET)) {
118 printf("Invalid CPLD register address\n");
119 return CMD_RET_USAGE;
120 }
121
122 if (argc == 3 && strcmp(argv[1], "read") == 0) {
123 printf("0x%x\n", cpld_read(dev, addr));
124 } else if (argc == 4 && strcmp(argv[1], "write") == 0) {
125 val = simple_strtoul(argv[3], NULL, 16);
126 cpld_write(dev, addr, val);
127 }
128
129 return 0;
130 }
131
132 U_BOOT_CMD(
133 cpld, 4, 1, do_cpld,
134 "CPLD access",
135 "info\n"
136 "cpld read addr\n"
137 "cpld write addr val\n"
138 );
139
renesas_ulcb_sysreset_request(struct udevice * dev,enum sysreset_t type)140 static int renesas_ulcb_sysreset_request(struct udevice *dev, enum sysreset_t type)
141 {
142 cpld_write(dev, CPLD_ADDR_RESET, 1);
143
144 return -EINPROGRESS;
145 }
146
renesas_ulcb_sysreset_probe(struct udevice * dev)147 static int renesas_ulcb_sysreset_probe(struct udevice *dev)
148 {
149 struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
150
151 if (gpio_request_by_name(dev, "gpio-miso", 0, &priv->miso,
152 GPIOD_IS_IN))
153 return -EINVAL;
154
155 if (gpio_request_by_name(dev, "gpio-sck", 0, &priv->sck,
156 GPIOD_IS_OUT))
157 return -EINVAL;
158
159 if (gpio_request_by_name(dev, "gpio-sstbz", 0, &priv->sstbz,
160 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE))
161 return -EINVAL;
162
163 if (gpio_request_by_name(dev, "gpio-mosi", 0, &priv->mosi,
164 GPIOD_IS_OUT))
165 return -EINVAL;
166
167 /* PULL-UP on MISO line */
168 setbits_le32(PFC_PUEN5, PUEN_SSI_SDATA4);
169
170 /* Dummy read */
171 cpld_read(dev, CPLD_ADDR_VERSION);
172
173 return 0;
174 }
175
176 static struct sysreset_ops renesas_ulcb_sysreset = {
177 .request = renesas_ulcb_sysreset_request,
178 };
179
180 static const struct udevice_id renesas_ulcb_sysreset_ids[] = {
181 { .compatible = "renesas,ulcb-cpld" },
182 { }
183 };
184
185 U_BOOT_DRIVER(sysreset_renesas_ulcb) = {
186 .name = "renesas_ulcb_sysreset",
187 .id = UCLASS_SYSRESET,
188 .ops = &renesas_ulcb_sysreset,
189 .probe = renesas_ulcb_sysreset_probe,
190 .of_match = renesas_ulcb_sysreset_ids,
191 .priv_auto = sizeof(struct renesas_ulcb_sysreset_priv),
192 };
193