1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright 2008 Freescale Semiconductor, Inc.
4  */
5 
6 #include <common.h>
7 
8 #include <fsl_ddr_sdram.h>
9 #include <fsl_ddr_dimm_params.h>
10 
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)11 void fsl_ddr_board_options(memctl_options_t *popts,
12 				dimm_params_t *pdimm,
13 				unsigned int ctrl_num)
14 {
15 	/*
16 	 * Factors to consider for clock adjust:
17 	 *	- number of chips on bus
18 	 *	- position of slot
19 	 *	- DDR1 vs. DDR2?
20 	 *	- ???
21 	 *
22 	 * This needs to be determined on a board-by-board basis.
23 	 *	0110	3/4 cycle late
24 	 *	0111	7/8 cycle late
25 	 */
26 	popts->clk_adjust = 7;
27 
28 	/*
29 	 * Factors to consider for CPO:
30 	 *	- frequency
31 	 *	- ddr1 vs. ddr2
32 	 */
33 	popts->cpo_override = 10;
34 
35 	/*
36 	 * Factors to consider for write data delay:
37 	 *	- number of DIMMs
38 	 *
39 	 * 1 = 1/4 clock delay
40 	 * 2 = 1/2 clock delay
41 	 * 3 = 3/4 clock delay
42 	 * 4 = 1   clock delay
43 	 * 5 = 5/4 clock delay
44 	 * 6 = 3/2 clock delay
45 	 */
46 	popts->write_data_delay = 3;
47 
48 	/*
49 	 * Factors to consider for half-strength driver enable:
50 	 *	- number of DIMMs installed
51 	 */
52 	popts->half_strength_driver_enable = 0;
53 }
54