1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Board functions for TI AM335X based rut board
4 * (C) Copyright 2013 Siemens Schweiz AG
5 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 *
7 * Based on:
8 * u-boot:/board/ti/am335x/board.c
9 *
10 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
11 */
12
13 #include <common.h>
14 #include <env.h>
15 #include <errno.h>
16 #include <init.h>
17 #include <malloc.h>
18 #include <net.h>
19 #include <spi.h>
20 #include <spl.h>
21 #include <asm/arch/cpu.h>
22 #include <asm/arch/hardware.h>
23 #include <asm/arch/omap.h>
24 #include <asm/arch/ddr_defs.h>
25 #include <asm/arch/clock.h>
26 #include <asm/arch/gpio.h>
27 #include <asm/arch/mmc_host_def.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/io.h>
30 #include <asm/emif.h>
31 #include <asm/gpio.h>
32 #include <i2c.h>
33 #include <miiphy.h>
34 #include <cpsw.h>
35 #include <video.h>
36 #include <watchdog.h>
37 #include <linux/delay.h>
38 #include "board.h"
39 #include "../common/factoryset.h"
40 #include "../../../drivers/video/da8xx-fb.h"
41
42 /*
43 * Read header information from EEPROM into global structure.
44 */
read_eeprom(void)45 static int read_eeprom(void)
46 {
47 return 0;
48 }
49
50 #ifdef CONFIG_SPL_BUILD
board_init_ddr(void)51 static void board_init_ddr(void)
52 {
53 struct emif_regs rut_ddr3_emif_reg_data = {
54 .sdram_config = 0x61C04AB2,
55 .sdram_tim1 = 0x0888A39B,
56 .sdram_tim2 = 0x26337FDA,
57 .sdram_tim3 = 0x501F830F,
58 .emif_ddr_phy_ctlr_1 = 0x6,
59 .zq_config = 0x50074BE4,
60 .ref_ctrl = 0x93B,
61 };
62
63 struct ddr_data rut_ddr3_data = {
64 .datardsratio0 = 0x3b,
65 .datawdsratio0 = 0x85,
66 .datafwsratio0 = 0x100,
67 .datawrsratio0 = 0xc1,
68 };
69
70 struct cmd_control rut_ddr3_cmd_ctrl_data = {
71 .cmd0csratio = 0x40,
72 .cmd0iclkout = 1,
73 .cmd1csratio = 0x40,
74 .cmd1iclkout = 1,
75 .cmd2csratio = 0x40,
76 .cmd2iclkout = 1,
77 };
78
79 const struct ctrl_ioregs ioregs = {
80 .cm0ioctl = RUT_IOCTRL_VAL,
81 .cm1ioctl = RUT_IOCTRL_VAL,
82 .cm2ioctl = RUT_IOCTRL_VAL,
83 .dt0ioctl = RUT_IOCTRL_VAL,
84 .dt1ioctl = RUT_IOCTRL_VAL,
85 };
86
87 config_ddr(DDR_PLL_FREQ, &ioregs, &rut_ddr3_data,
88 &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
89 }
90
request_and_pulse_reset(int gpio,const char * name)91 static int request_and_pulse_reset(int gpio, const char *name)
92 {
93 int ret;
94 const int delay_us = 2000; /* 2ms */
95
96 ret = gpio_request(gpio, name);
97 if (ret < 0) {
98 printf("%s: Unable to request %s\n", __func__, name);
99 goto err;
100 }
101
102 ret = gpio_direction_output(gpio, 0);
103 if (ret < 0) {
104 printf("%s: Unable to set %s as output\n", __func__, name);
105 goto err_free_gpio;
106 }
107
108 udelay(delay_us);
109
110 gpio_set_value(gpio, 1);
111
112 return 0;
113
114 err_free_gpio:
115 gpio_free(gpio);
116 err:
117 return ret;
118 }
119
120 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
121 #define ETH_PHY_RESET_GPIO GPIO_TO_PIN(2, 18)
122 #define MAXTOUCH_RESET_GPIO GPIO_TO_PIN(3, 18)
123 #define DISPLAY_RESET_GPIO GPIO_TO_PIN(3, 19)
124
125 #define REQUEST_AND_PULSE_RESET(N) \
126 request_and_pulse_reset(N, #N);
127
spl_siemens_board_init(void)128 static void spl_siemens_board_init(void)
129 {
130 REQUEST_AND_PULSE_RESET(ETH_PHY_RESET_GPIO);
131 REQUEST_AND_PULSE_RESET(MAXTOUCH_RESET_GPIO);
132 REQUEST_AND_PULSE_RESET(DISPLAY_RESET_GPIO);
133 }
134 #endif /* if def CONFIG_SPL_BUILD */
135
136 #if defined(CONFIG_DRIVER_TI_CPSW)
cpsw_control(int enabled)137 static void cpsw_control(int enabled)
138 {
139 /* VTP can be added here */
140
141 return;
142 }
143
144 static struct cpsw_slave_data cpsw_slaves[] = {
145 {
146 .slave_reg_ofs = 0x208,
147 .sliver_reg_ofs = 0xd80,
148 .phy_addr = 1,
149 .phy_if = PHY_INTERFACE_MODE_RMII,
150 },
151 {
152 .slave_reg_ofs = 0x308,
153 .sliver_reg_ofs = 0xdc0,
154 .phy_addr = 0,
155 .phy_if = PHY_INTERFACE_MODE_RMII,
156 },
157 };
158
159 static struct cpsw_platform_data cpsw_data = {
160 .mdio_base = CPSW_MDIO_BASE,
161 .cpsw_base = CPSW_BASE,
162 .mdio_div = 0xff,
163 .channels = 8,
164 .cpdma_reg_ofs = 0x800,
165 .slaves = 1,
166 .slave_data = cpsw_slaves,
167 .ale_reg_ofs = 0xd00,
168 .ale_entries = 1024,
169 .host_port_reg_ofs = 0x108,
170 .hw_stats_reg_ofs = 0x900,
171 .bd_ram_ofs = 0x2000,
172 .mac_control = (1 << 5),
173 .control = cpsw_control,
174 .host_port_num = 0,
175 .version = CPSW_CTRL_VERSION_2,
176 };
177
178 #if defined(CONFIG_DRIVER_TI_CPSW) || \
179 (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
board_eth_init(struct bd_info * bis)180 int board_eth_init(struct bd_info *bis)
181 {
182 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
183 int n = 0;
184 int rv;
185
186 #ifndef CONFIG_SPL_BUILD
187 factoryset_env_set();
188 #endif
189
190 /* Set rgmii mode and enable rmii clock to be sourced from chip */
191 writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
192
193 rv = cpsw_register(&cpsw_data);
194 if (rv < 0)
195 printf("Error %d registering CPSW switch\n", rv);
196 else
197 n += rv;
198 return n;
199 }
200 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
201 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
202
203 #if defined(CONFIG_HW_WATCHDOG)
204 static bool hw_watchdog_init_done;
205 static int hw_watchdog_trigger_level;
206
hw_watchdog_reset(void)207 void hw_watchdog_reset(void)
208 {
209 if (!hw_watchdog_init_done)
210 return;
211
212 hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1;
213 gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
214 }
215
hw_watchdog_init(void)216 void hw_watchdog_init(void)
217 {
218 gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger");
219 gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
220
221 hw_watchdog_reset();
222
223 hw_watchdog_init_done = 1;
224 }
225 #endif /* defined(CONFIG_HW_WATCHDOG) */
226
227 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
228 static struct da8xx_panel lcd_panels[] = {
229 /* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */
230 [0] = {
231 .name = "KWH043MC17-F01",
232 .width = 480,
233 .height = 800,
234 .hfp = 50, /* no spec, "don't care" values */
235 .hbp = 50,
236 .hsw = 50,
237 .vfp = 50,
238 .vbp = 50,
239 .vsw = 50,
240 .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
241 .invert_pxl_clk = 1,
242 },
243 /* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */
244 [1] = {
245 .name = "KWH043ST20-F01",
246 .width = 480,
247 .height = 800,
248 .hfp = 50, /* no spec, "don't care" values */
249 .hbp = 50,
250 .hsw = 50,
251 .vfp = 50,
252 .vbp = 50,
253 .vsw = 50,
254 .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
255 .invert_pxl_clk = 1,
256 },
257 /* Multi-Inno, 4.3", 480x800, MI0430VT-1 */
258 [2] = {
259 .name = "MI0430VT-1",
260 .width = 480,
261 .height = 800,
262 .hfp = 50, /* no spec, "don't care" values */
263 .hbp = 50,
264 .hsw = 50,
265 .vfp = 50,
266 .vbp = 50,
267 .vsw = 50,
268 .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
269 .invert_pxl_clk = 1,
270 },
271 };
272
273 static const struct display_panel disp_panels[] = {
274 [0] = {
275 WVGA,
276 16, /* RGB 888 */
277 16,
278 COLOR_ACTIVE,
279 },
280 [1] = {
281 WVGA,
282 16, /* RGB 888 */
283 16,
284 COLOR_ACTIVE,
285 },
286 [2] = {
287 WVGA,
288 24, /* RGB 888 */
289 16,
290 COLOR_ACTIVE,
291 },
292 };
293
294 static const struct lcd_ctrl_config lcd_cfgs[] = {
295 [0] = {
296 &disp_panels[0],
297 .ac_bias = 255,
298 .ac_bias_intrpt = 0,
299 .dma_burst_sz = 16,
300 .bpp = 16,
301 .fdd = 0x80,
302 .tft_alt_mode = 0,
303 .stn_565_mode = 0,
304 .mono_8bit_mode = 0,
305 .invert_line_clock = 1,
306 .invert_frm_clock = 1,
307 .sync_edge = 0,
308 .sync_ctrl = 1,
309 .raster_order = 0,
310 },
311 [1] = {
312 &disp_panels[1],
313 .ac_bias = 255,
314 .ac_bias_intrpt = 0,
315 .dma_burst_sz = 16,
316 .bpp = 16,
317 .fdd = 0x80,
318 .tft_alt_mode = 0,
319 .stn_565_mode = 0,
320 .mono_8bit_mode = 0,
321 .invert_line_clock = 1,
322 .invert_frm_clock = 1,
323 .sync_edge = 0,
324 .sync_ctrl = 1,
325 .raster_order = 0,
326 },
327 [2] = {
328 &disp_panels[2],
329 .ac_bias = 255,
330 .ac_bias_intrpt = 0,
331 .dma_burst_sz = 16,
332 .bpp = 24,
333 .fdd = 0x80,
334 .tft_alt_mode = 0,
335 .stn_565_mode = 0,
336 .mono_8bit_mode = 0,
337 .invert_line_clock = 1,
338 .invert_frm_clock = 1,
339 .sync_edge = 0,
340 .sync_ctrl = 1,
341 .raster_order = 0,
342 },
343
344 };
345
346 /* no console on this board */
board_cfb_skip(void)347 int board_cfb_skip(void)
348 {
349 return 1;
350 }
351
352 #define PLL_GET_M(v) ((v >> 8) & 0x7ff)
353 #define PLL_GET_N(v) (v & 0x7f)
354
355 static struct dpll_regs dpll_lcd_regs = {
356 .cm_clkmode_dpll = CM_WKUP + 0x98,
357 .cm_idlest_dpll = CM_WKUP + 0x48,
358 .cm_clksel_dpll = CM_WKUP + 0x54,
359 };
360
get_clk(struct dpll_regs * dpll_regs)361 static int get_clk(struct dpll_regs *dpll_regs)
362 {
363 unsigned int val;
364 unsigned int m, n;
365 int f = 0;
366
367 val = readl(dpll_regs->cm_clksel_dpll);
368 m = PLL_GET_M(val);
369 n = PLL_GET_N(val);
370 f = (m * V_OSCK) / n;
371
372 return f;
373 };
374
clk_get(int clk)375 int clk_get(int clk)
376 {
377 return get_clk(&dpll_lcd_regs);
378 };
379
conf_disp_pll(int m,int n)380 static int conf_disp_pll(int m, int n)
381 {
382 struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
383 struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
384 #if defined(DISPL_PLL_SPREAD_SPECTRUM)
385 struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
386 #endif
387
388 u32 *const clk_domains[] = {
389 &cmper->lcdclkctrl,
390 0
391 };
392 u32 *const clk_modules_explicit_en[] = {
393 &cmper->lcdclkctrl,
394 &cmper->lcdcclkstctrl,
395 &cmper->spi1clkctrl,
396 0
397 };
398 do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
399
400 do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
401
402 #if defined(DISPL_PLL_SPREAD_SPECTRUM)
403 writel(0x64, &cmwkup->resv6[3]); /* 0x50 */
404 writel(0x800, &cmwkup->resv6[2]); /* 0x4c */
405 writel(readl(&cmwkup->clkmoddplldisp) | CM_CLKMODE_DPLL_SSC_EN_MASK,
406 &cmwkup->clkmoddplldisp); /* 0x98 */
407 #endif
408 return 0;
409 }
410
set_gpio(int gpio,int state)411 static int set_gpio(int gpio, int state)
412 {
413 gpio_request(gpio, "temp");
414 gpio_direction_output(gpio, state);
415 gpio_set_value(gpio, state);
416 gpio_free(gpio);
417 return 0;
418 }
419
enable_lcd(void)420 static int enable_lcd(void)
421 {
422 unsigned char buf[1];
423
424 set_gpio(BOARD_LCD_RESET, 0);
425 mdelay(1);
426 set_gpio(BOARD_LCD_RESET, 1);
427 mdelay(1);
428
429 /* spi lcd init */
430 kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_0);
431
432 /* backlight on */
433 buf[0] = 0xf;
434 i2c_write(0x24, 0x7, 1, buf, 1);
435 buf[0] = 0x3f;
436 i2c_write(0x24, 0x8, 1, buf, 1);
437 return 0;
438 }
439
arch_early_init_r(void)440 int arch_early_init_r(void)
441 {
442 enable_lcd();
443 return 0;
444 }
445
board_video_init(void)446 static int board_video_init(void)
447 {
448 int i;
449 int anzdisp = ARRAY_SIZE(lcd_panels);
450 int display = 1;
451
452 for (i = 0; i < anzdisp; i++) {
453 if (strncmp((const char *)factory_dat.disp_name,
454 lcd_panels[i].name,
455 strlen((const char *)factory_dat.disp_name)) == 0) {
456 printf("DISPLAY: %s\n", factory_dat.disp_name);
457 break;
458 }
459 }
460 if (i == anzdisp) {
461 i = 1;
462 printf("%s: %s not found, using default %s\n", __func__,
463 factory_dat.disp_name, lcd_panels[i].name);
464 }
465 conf_disp_pll(24, 1);
466 da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display],
467 lcd_cfgs[display].bpp);
468
469 return 0;
470 }
471 #endif /* ifdef CONFIG_VIDEO */
472
473 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)474 int board_late_init(void)
475 {
476 int ret;
477 char tmp[2 * MAX_STRING_LENGTH + 2];
478
479 omap_nand_switch_ecc(1, 8);
480
481 if (factory_dat.asn[0] != 0)
482 sprintf(tmp, "%s_%s", factory_dat.asn,
483 factory_dat.comp_version);
484 else
485 strcpy(tmp, "QMX7.E38_4.0");
486
487 ret = env_set("boardid", tmp);
488 if (ret)
489 printf("error setting board id\n");
490
491 return 0;
492 }
493 #endif
494
495 #include "../common/board.c"
496