1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Board functions for Siemens TAURUS (AT91SAM9G20) based boards
4 * (C) Copyright Siemens AG
5 *
6 * Based on:
7 * U-Boot file: board/atmel/at91sam9260ek/at91sam9260ek.c
8 *
9 * (C) Copyright 2007-2008
10 * Stelian Pop <stelian@popies.net>
11 * Lead Tech Design <www.leadtechdesign.com>
12 */
13
14 #include <command.h>
15 #include <common.h>
16 #include <dm.h>
17 #include <env.h>
18 #include <flash.h>
19 #include <init.h>
20 #include <asm/global_data.h>
21 #include <asm/io.h>
22 #include <asm/arch/at91sam9260_matrix.h>
23 #include <asm/arch/at91sam9_smc.h>
24 #include <asm/arch/at91_common.h>
25 #include <asm/arch/at91_rstc.h>
26 #include <asm/arch/gpio.h>
27 #include <asm/arch/at91sam9_sdramc.h>
28 #include <asm/arch/atmel_serial.h>
29 #include <asm/arch/clk.h>
30 #include <asm/gpio.h>
31 #include <linux/mtd/rawnand.h>
32 #include <atmel_mci.h>
33 #include <asm/arch/at91_spi.h>
34 #include <spi.h>
35
36 #include <net.h>
37 #ifndef CONFIG_DM_ETH
38 #include <netdev.h>
39 #endif
40
41 DECLARE_GLOBAL_DATA_PTR;
42
taurus_request_gpio(void)43 static void taurus_request_gpio(void)
44 {
45 gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
46 gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
47 gpio_request(AT91_PIN_PA25, "ena PHY");
48 }
49
taurus_nand_hw_init(void)50 static void taurus_nand_hw_init(void)
51 {
52 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
53 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
54 unsigned long csa;
55
56 /* Assign CS3 to NAND/SmartMedia Interface */
57 csa = readl(&matrix->ebicsa);
58 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
59 writel(csa, &matrix->ebicsa);
60
61 /* Configure SMC CS3 for NAND/SmartMedia */
62 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
63 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
64 &smc->cs[3].setup);
65 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
66 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(3),
67 &smc->cs[3].pulse);
68 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
69 &smc->cs[3].cycle);
70 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
71 AT91_SMC_MODE_EXNW_DISABLE |
72 AT91_SMC_MODE_DBW_8 |
73 AT91_SMC_MODE_TDF_CYCLE(3),
74 &smc->cs[3].mode);
75
76 /* Configure RDY/BSY */
77 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
78
79 /* Enable NandFlash */
80 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
81 }
82
83 #if defined(CONFIG_SPL_BUILD)
84 #include <spl.h>
85 #include <nand.h>
86 #include <spi_flash.h>
87
matrix_init(void)88 void matrix_init(void)
89 {
90 struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
91
92 writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
93 | AT91_MATRIX_SLOT_CYCLE_(0x40),
94 &mat->scfg[3]);
95 }
96
97 #if defined(CONFIG_BOARD_AXM)
at91_is_recovery(void)98 static int at91_is_recovery(void)
99 {
100 if ((at91_get_gpio_value(AT91_PIN_PA26) == 0) &&
101 (at91_get_gpio_value(AT91_PIN_PA27) == 0))
102 return 1;
103
104 return 0;
105 }
106 #elif defined(CONFIG_BOARD_TAURUS)
at91_is_recovery(void)107 static int at91_is_recovery(void)
108 {
109 if (at91_get_gpio_value(AT91_PIN_PA31) == 0)
110 return 1;
111
112 return 0;
113 }
114 #endif
115
spl_board_init(void)116 void spl_board_init(void)
117 {
118 taurus_nand_hw_init();
119 at91_spi0_hw_init(TAURUS_SPI_MASK);
120
121 #if defined(CONFIG_BOARD_AXM)
122 /* Configure LED PINs */
123 at91_set_gpio_output(AT91_PIN_PA6, 0);
124 at91_set_gpio_output(AT91_PIN_PA8, 0);
125 at91_set_gpio_output(AT91_PIN_PA9, 0);
126 at91_set_gpio_output(AT91_PIN_PA10, 0);
127 at91_set_gpio_output(AT91_PIN_PA11, 0);
128 at91_set_gpio_output(AT91_PIN_PA12, 0);
129
130 /* Configure recovery button PINs */
131 at91_set_gpio_input(AT91_PIN_PA26, 1);
132 at91_set_gpio_input(AT91_PIN_PA27, 1);
133 #elif defined(CONFIG_BOARD_TAURUS)
134 at91_set_gpio_input(AT91_PIN_PA31, 1);
135 #endif
136
137 /* check for recovery mode */
138 if (at91_is_recovery() == 1) {
139 struct spi_flash *flash;
140
141 puts("Recovery button pressed\n");
142 nand_init();
143 spl_nand_erase_one(0, 0);
144 flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
145 0,
146 CONFIG_SF_DEFAULT_SPEED,
147 CONFIG_SF_DEFAULT_MODE);
148 if (!flash) {
149 puts("no flash\n");
150 } else {
151 puts("erase spi flash sector 0\n");
152 spi_flash_erase(flash, 0,
153 CONFIG_SYS_NAND_U_BOOT_SIZE);
154 }
155 }
156 }
157
158 #define SDRAM_BASE_CONF (AT91_SDRAMC_NR_13 | AT91_SDRAMC_CAS_3 \
159 |AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \
160 | AT91_SDRAMC_TWR_VAL(3) | AT91_SDRAMC_TRC_VAL(9) \
161 | AT91_SDRAMC_TRP_VAL(3) | AT91_SDRAMC_TRCD_VAL(3) \
162 | AT91_SDRAMC_TRAS_VAL(6) | AT91_SDRAMC_TXSR_VAL(10))
163
sdramc_configure(unsigned int mask)164 void sdramc_configure(unsigned int mask)
165 {
166 struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX;
167 struct sdramc_reg setting;
168
169 at91_sdram_hw_init();
170 setting.cr = SDRAM_BASE_CONF | mask;
171 setting.mdr = AT91_SDRAMC_MD_SDRAM;
172 setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000;
173
174 writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC |
175 AT91_MATRIX_VDDIOMSEL_3_3V | AT91_MATRIX_EBI_IOSR_SEL,
176 &ma->ebicsa);
177
178 sdramc_initialize(ATMEL_BASE_CS1, &setting);
179 }
180
mem_init(void)181 void mem_init(void)
182 {
183 unsigned int ram_size = 0;
184
185 /* Configure SDRAM for 128MB */
186 sdramc_configure(AT91_SDRAMC_NC_10);
187
188 /* Do memtest for 128MB */
189 ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
190 CONFIG_SYS_SDRAM_SIZE);
191
192 /*
193 * If 32MB or 16MB should be supported check also for
194 * expected mirroring at A16 and A17
195 * To find mirror addresses depends how the collumns are connected
196 * at RAM (internaly or externaly)
197 * If the collumns are not in inverted order the mirror size effect
198 * behaves like normal SRAM with A0,A1,A2,etc. connected incremantal
199 */
200
201 /* Mirrors at A15 on ATMEL G20 SDRAM Controller with 64MB*/
202 if (ram_size == 0x800) {
203 printf("\n\r 64MB\n");
204 sdramc_configure(AT91_SDRAMC_NC_9);
205 } else {
206 /* Size already initialized */
207 printf("\n\r 128MB\n");
208 }
209 }
210 #endif
211
212 #ifdef CONFIG_MACB
siemens_phy_reset(void)213 static void siemens_phy_reset(void)
214 {
215 /*
216 * we need to reset PHY for 200us
217 * because of bug in ATMEL G20 CPU (undefined initial state of GPIO)
218 */
219 if ((readl(AT91_ASM_RSTC_SR) & AT91_RSTC_RSTTYP) ==
220 AT91_RSTC_RSTTYP_GENERAL)
221 at91_set_gpio_value(AT91_PIN_PA25, 0); /* reset eth switch */
222 }
223
taurus_macb_hw_init(void)224 static void taurus_macb_hw_init(void)
225 {
226 /* Enable EMAC clock */
227 at91_periph_clk_enable(ATMEL_ID_EMAC0);
228
229 /*
230 * Disable pull-up on:
231 * RXDV (PA17) => PHY normal mode (not Test mode)
232 * ERX0 (PA14) => PHY ADDR0
233 * ERX1 (PA15) => PHY ADDR1
234 * ERX2 (PA25) => PHY ADDR2
235 * ERX3 (PA26) => PHY ADDR3
236 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
237 *
238 * PHY has internal pull-down
239 */
240 at91_set_pio_pullup(AT91_PIO_PORTA, 14, 0);
241 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
242 at91_set_pio_pullup(AT91_PIO_PORTA, 17, 0);
243 at91_set_pio_pullup(AT91_PIO_PORTA, 25, 0);
244 at91_set_pio_pullup(AT91_PIO_PORTA, 26, 0);
245 at91_set_pio_pullup(AT91_PIO_PORTA, 28, 0);
246
247 siemens_phy_reset();
248
249 at91_phy_reset();
250
251 at91_set_gpio_input(AT91_PIN_PA25, 1); /* ERST tri-state */
252
253 /* Re-enable pull-up */
254 at91_set_pio_pullup(AT91_PIO_PORTA, 14, 1);
255 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
256 at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
257 at91_set_pio_pullup(AT91_PIO_PORTA, 25, 1);
258 at91_set_pio_pullup(AT91_PIO_PORTA, 26, 1);
259 at91_set_pio_pullup(AT91_PIO_PORTA, 28, 1);
260
261 /* Initialize EMAC=MACB hardware */
262 at91_macb_hw_init();
263 }
264 #endif
265
266 #ifdef CONFIG_GENERIC_ATMEL_MCI
board_mmc_init(struct bd_info * bd)267 int board_mmc_init(struct bd_info *bd)
268 {
269 at91_mci_hw_init();
270
271 return atmel_mci_init((void *)ATMEL_BASE_MCI);
272 }
273 #endif
274
board_early_init_f(void)275 int board_early_init_f(void)
276 {
277 /* Enable clocks for all PIOs */
278 at91_periph_clk_enable(ATMEL_ID_PIOA);
279 at91_periph_clk_enable(ATMEL_ID_PIOB);
280 at91_periph_clk_enable(ATMEL_ID_PIOC);
281
282 at91_seriald_hw_init();
283 taurus_request_gpio();
284
285 return 0;
286 }
287
288 #ifdef CONFIG_USB_GADGET_AT91
289 #include <linux/usb/at91_udc.h>
290
at91_udp_hw_init(void)291 void at91_udp_hw_init(void)
292 {
293 /* Enable PLLB */
294 at91_pllb_clk_enable(get_pllb_init());
295
296 /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
297 at91_periph_clk_enable(ATMEL_ID_UDP);
298
299 at91_system_clk_enable(AT91SAM926x_PMC_UDP);
300 }
301
302 struct at91_udc_data board_udc_data = {
303 .baseaddr = ATMEL_BASE_UDP0,
304 };
305 #endif
306
board_init(void)307 int board_init(void)
308 {
309 /* adress of boot parameters */
310 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
311
312 taurus_request_gpio();
313 #ifdef CONFIG_CMD_NAND
314 taurus_nand_hw_init();
315 #endif
316 #ifdef CONFIG_MACB
317 taurus_macb_hw_init();
318 #endif
319 at91_spi0_hw_init(TAURUS_SPI_MASK);
320 #ifdef CONFIG_USB_GADGET_AT91
321 at91_udp_hw_init();
322 at91_udc_probe(&board_udc_data);
323 #endif
324
325 return 0;
326 }
327
dram_init(void)328 int dram_init(void)
329 {
330 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
331 CONFIG_SYS_SDRAM_SIZE);
332 return 0;
333 }
334
335 #if !defined(CONFIG_SPL_BUILD)
336 #if defined(CONFIG_BOARD_AXM)
337 /*
338 * Booting the Fallback Image.
339 *
340 * The function is used to provide and
341 * boot the image with the fallback
342 * parameters, incase if the faulty image
343 * in upgraded over the base firmware.
344 *
345 */
upgrade_failure_fallback(void)346 static int upgrade_failure_fallback(void)
347 {
348 char *partitionset_active = NULL;
349 char *rootfs = NULL;
350 char *rootfs_fallback = NULL;
351 char *kern_off;
352 char *kern_off_fb;
353 char *kern_size;
354 char *kern_size_fb;
355
356 partitionset_active = env_get("partitionset_active");
357 if (partitionset_active) {
358 if (partitionset_active[0] == 'A')
359 env_set("partitionset_active", "B");
360 else
361 env_set("partitionset_active", "A");
362 } else {
363 printf("partitionset_active missing.\n");
364 return -ENOENT;
365 }
366
367 rootfs = env_get("rootfs");
368 rootfs_fallback = env_get("rootfs_fallback");
369 env_set("rootfs", rootfs_fallback);
370 env_set("rootfs_fallback", rootfs);
371
372 kern_size = env_get("kernel_size");
373 kern_size_fb = env_get("kernel_size_fallback");
374 env_set("kernel_size", kern_size_fb);
375 env_set("kernel_size_fallback", kern_size);
376
377 kern_off = env_get("kernel_Off");
378 kern_off_fb = env_get("kernel_Off_fallback");
379 env_set("kernel_Off", kern_off_fb);
380 env_set("kernel_Off_fallback", kern_off);
381
382 env_set("bootargs", '\0');
383 env_set("upgrade_available", '\0');
384 env_set("boot_retries", '\0');
385 env_save();
386
387 return 0;
388 }
389
do_upgrade_available(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])390 static int do_upgrade_available(struct cmd_tbl *cmdtp, int flag, int argc,
391 char *const argv[])
392 {
393 unsigned long upgrade_available = 0;
394 unsigned long boot_retry = 0;
395 char boot_buf[10];
396
397 upgrade_available = simple_strtoul(env_get("upgrade_available"), NULL,
398 10);
399 if (upgrade_available) {
400 boot_retry = simple_strtoul(env_get("boot_retries"), NULL, 10);
401 boot_retry++;
402 sprintf(boot_buf, "%lx", boot_retry);
403 env_set("boot_retries", boot_buf);
404 env_save();
405
406 /*
407 * Here the boot_retries count is checked, and if the
408 * count becomes greater than 2 switch back to the
409 * fallback, and reset the board.
410 */
411
412 if (boot_retry > 2) {
413 if (upgrade_failure_fallback() == 0)
414 do_reset(NULL, 0, 0, NULL);
415 return -1;
416 }
417 }
418 return 0;
419 }
420
421 U_BOOT_CMD(
422 upgrade_available, 1, 1, do_upgrade_available,
423 "check Siemens update",
424 "no parameters"
425 );
426 #endif
427 #endif
428