1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2018 NXP
4 */
5
6 #include <common.h>
7 #include <hang.h>
8 #include <init.h>
9 #include <log.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/ddr.h>
12 #include <asm/arch/imx8mq_pins.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/global_data.h>
15 #include <asm/io.h>
16 #include <asm/mach-imx/gpio.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <linux/delay.h>
20 #include <errno.h>
21 #include <fsl_esdhc_imx.h>
22 #include <mmc.h>
23 #include <spl.h>
24
25 #include "lpddr4_timing.h"
26
27 DECLARE_GLOBAL_DATA_PTR;
28
29 #define DDR_DET_1 IMX_GPIO_NR(3, 11)
30 #define DDR_DET_2 IMX_GPIO_NR(3, 12)
31 #define DDR_DET_3 IMX_GPIO_NR(3, 13)
32
33 static iomux_v3_cfg_t const verdet_pads[] = {
34 IMX8MQ_PAD_NAND_DATA01__GPIO3_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL),
35 IMX8MQ_PAD_NAND_DATA02__GPIO3_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL),
36 IMX8MQ_PAD_NAND_DATA03__GPIO3_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
37 IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
38 IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
39 IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
40 IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
41 };
42
43 /*
44 * DDR_DET_1 DDR_DET_2 DDR_DET_3
45 * 0 0 1 4G LPDDR4
46 * 1 1 1 3G LPDDR4
47 * 1 1 0 2G LPDDR4
48 * 1 0 1 1G LPDDR4
49 */
spl_dram_init(void)50 static void spl_dram_init(void)
51 {
52 struct dram_timing_info *dram_timing;
53 u8 ddr = 0, size;
54
55 imx_iomux_v3_setup_multiple_pads(verdet_pads, ARRAY_SIZE(verdet_pads));
56
57 gpio_request(DDR_DET_1, "ddr_det_1");
58 gpio_direction_input(DDR_DET_1);
59 gpio_request(DDR_DET_2, "ddr_det_2");
60 gpio_direction_input(DDR_DET_2);
61 gpio_request(DDR_DET_3, "ddr_det_3");
62 gpio_direction_input(DDR_DET_3);
63
64 ddr |= !!gpio_get_value(DDR_DET_3) << 0;
65 ddr |= !!gpio_get_value(DDR_DET_2) << 1;
66 ddr |= !!gpio_get_value(DDR_DET_1) << 2;
67
68 switch (ddr) {
69 case 0x1:
70 size = 4;
71 dram_timing = &dram_timing_4gb;
72 break;
73 case 0x7:
74 size = 3;
75 dram_timing = &dram_timing_3gb;
76 break;
77 case 0x6:
78 size = 2;
79 dram_timing = &dram_timing_2gb;
80 break;
81 case 0x5:
82 size = 1;
83 dram_timing = &dram_timing_1gb;
84 break;
85 default:
86 puts("Unknown DDR type!!!\n");
87 return;
88 }
89
90 printf("%s: LPDDR4 %d GiB\n", __func__, size);
91 ddr_init(dram_timing);
92 writel(size, M4_BOOTROM_BASE_ADDR);
93 }
94
95 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
96 #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
97 #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
98
board_mmc_getcd(struct mmc * mmc)99 int board_mmc_getcd(struct mmc *mmc)
100 {
101 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
102 int ret = 0;
103
104 switch (cfg->esdhc_base) {
105 case USDHC1_BASE_ADDR:
106 ret = 1;
107 break;
108 case USDHC2_BASE_ADDR:
109 ret = !gpio_get_value(USDHC2_CD_GPIO);
110 return ret;
111 }
112
113 return 1;
114 }
115
116 #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
117 PAD_CTL_FSEL2)
118 #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
119
120 static iomux_v3_cfg_t const usdhc1_pads[] = {
121 IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
122 IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
123 IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
124 IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
125 IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
126 IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
127 IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
128 IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
129 IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
130 IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
131 IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
132 };
133
134 static iomux_v3_cfg_t const usdhc2_pads[] = {
135 IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
137 IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
138 IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
139 IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
140 IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
142 IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
143 };
144
145 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
146 {USDHC1_BASE_ADDR, 0, 8},
147 {USDHC2_BASE_ADDR, 0, 4},
148 };
149
board_mmc_init(struct bd_info * bis)150 int board_mmc_init(struct bd_info *bis)
151 {
152 int ret;
153 /*
154 * According to the board_mmc_init() the following map is done:
155 * (U-Boot device node) (Physical Port)
156 * mmc0 USDHC1
157 * mmc1 USDHC2
158 */
159 init_clk_usdhc(0);
160 usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
161 imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
162 gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
163 gpio_direction_output(USDHC1_PWR_GPIO, 0);
164 udelay(500);
165 gpio_direction_output(USDHC1_PWR_GPIO, 1);
166 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
167 if (ret)
168 return ret;
169
170 init_clk_usdhc(1);
171 usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
172 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
173 gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
174 gpio_direction_output(USDHC2_PWR_GPIO, 0);
175 udelay(500);
176 gpio_direction_output(USDHC2_PWR_GPIO, 1);
177 return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
178 }
179
spl_board_init(void)180 void spl_board_init(void)
181 {
182 puts("Normal Boot\n");
183 }
184
185 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)186 int board_fit_config_name_match(const char *name)
187 {
188 /* Just empty function now - can't decide what to choose */
189 debug("%s: %s\n", __func__, name);
190
191 return 0;
192 }
193 #endif
194
board_init_f(ulong dummy)195 void board_init_f(ulong dummy)
196 {
197 int ret;
198
199 /* Clear global data */
200 memset((void *)gd, 0, sizeof(gd_t));
201
202 arch_cpu_init();
203
204 init_uart_clk(0);
205
206 board_early_init_f();
207
208 timer_init();
209
210 preloader_console_init();
211
212 /* Clear the BSS. */
213 memset(__bss_start, 0, __bss_end - __bss_start);
214
215 ret = spl_init();
216 if (ret) {
217 debug("spl_init() failed: %d\n", ret);
218 hang();
219 }
220
221 enable_tzc380();
222
223 /* DDR initialization */
224 spl_dram_init();
225
226 board_init_r(NULL, 0);
227 }
228