1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Embest/Timll DevKit3250 board support
4  *
5  * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
6  */
7 
8 #include <common.h>
9 #include <init.h>
10 #include <asm/arch/sys_proto.h>
11 #include <asm/arch/clk.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/emc.h>
14 #include <asm/arch/wdt.h>
15 #include <asm/global_data.h>
16 #include <asm/io.h>
17 #include <linux/delay.h>
18 
19 DECLARE_GLOBAL_DATA_PTR;
20 
21 static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
22 static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
23 static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
24 
reset_periph(void)25 void reset_periph(void)
26 {
27 	/* This function resets peripherals by triggering RESOUT_N */
28 	setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
29 	writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl);
30 	udelay(300);
31 
32 	writel(0, &wdt->mctrl);
33 	clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
34 
35 	/* Such a long delay is needed to initialize SMSC phy */
36 	udelay(10000);
37 }
38 
board_early_init_f(void)39 int board_early_init_f(void)
40 {
41 	lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
42 	lpc32xx_i2c_init(1);
43 	lpc32xx_i2c_init(2);
44 	lpc32xx_ssp_init();
45 	lpc32xx_mac_init();
46 
47 	/*
48 	 * nWP may be controlled by GPO19, but unpopulated by default R23
49 	 * makes no sense to configure this GPIO level, nWP is always high
50 	 */
51 	lpc32xx_slc_nand_init();
52 
53 	return 0;
54 }
55 
board_init(void)56 int board_init(void)
57 {
58 	/* adress of boot parameters */
59 	gd->bd->bi_boot_params  = CONFIG_SYS_SDRAM_BASE + 0x100;
60 
61 #ifdef CONFIG_SYS_FLASH_CFI
62 	/* Use 16-bit memory interface for NOR Flash */
63 	emc->stat[0].config	= EMC_STAT_CONFIG_PB | EMC_STAT_CONFIG_16BIT;
64 
65 	/* Change the NOR timings to optimum value to get maximum bandwidth */
66 	emc->stat[0].waitwen	= EMC_STAT_WAITWEN(1);
67 	emc->stat[0].waitoen	= EMC_STAT_WAITOEN(0);
68 	emc->stat[0].waitrd	= EMC_STAT_WAITRD(12);
69 	emc->stat[0].waitpage	= EMC_STAT_WAITPAGE(12);
70 	emc->stat[0].waitwr	= EMC_STAT_WAITWR(5);
71 	emc->stat[0].waitturn	= EMC_STAT_WAITTURN(2);
72 #endif
73 
74 	return 0;
75 }
76 
dram_init(void)77 int dram_init(void)
78 {
79 	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
80 				    CONFIG_SYS_SDRAM_SIZE);
81 
82 	return 0;
83 }
84